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PSout
A
When a prescale value of 1 is chosen ( ECCTL1[13:9] = 0,0,0,0,0 ) the input capture signal by-passes the prescale
logic completely.
ECAPx
PSout
div 2
PSout
div 4
PSout
div 6
PSout
div 8
PSout
div 10
8.4.2 Edge Polarity Select and Qualifier
•
Four independent edge polarity (rising edge/falling edge) selection MUXes are used, one for each
capture event.
•
Each edge (up to 4) is event qualified by the Modulo4 sequencer.
•
The edge event is gated to its respective CAPx register by the Mod4 counter. The CAPx register is
loaded on the falling edge.
8.4.3 Continuous/One-Shot Control
•
The Mod4 (2 bit) counter is incremented via edge qualified events (CEVT1-CEVT4).
•
The Mod4 counter continues counting (0->1->2->3->0) and wraps around unless stopped.
•
A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4
counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation.
SPRUH22I – April 2012 – Revised November 2019
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Figure 8-4. Event Prescale Control
Event prescaler
0
1
/n
5
By−pass
ECCTL1[EVTPS]
prescaler [5 bits]
(counter)
Figure 8-5. Prescale Function Waveforms
Copyright © 2012–2019, Texas Instruments Incorporated
Capture Mode Description
ECAPx pin
(from GPIO)
C28 Enhanced Capture (eCAP) Module
795
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