I2C Master Masked Interrupt Status (I2Cmmis), Offset 0X018; I2C Master Interrupt Clear (I2Cmicr), Offset 0X01C; I2C Master Masked Interrupt Status (I2Cmmis) Register; I2C Master Interrupt Clear (I2Cmicr) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

22.6.7 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018

The I2C Master Masked Interrupt Status (I2CMMIS) register specifies whether an interrupt was signaled. It
is shown and described in the figure and table below.
Figure 22-21. I2C Master Masked Interrupt Status (I2CMMIS) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-11. I2C Master Masked Interrupt Status (I2CMMIS) Register Field Descriptions
Bit Field
31-1 Reserved
0 MIS

22.6.8 I2C Master Interrupt Clear (I2CMICR), offset 0x01C

The I2C Master Interrupt Clear (I2CMICR) register clears the raw and masked interrupts. It is shown and
described in the figure and table below.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-12. I2C Master Interrupt Clear (I2CMICR) Register Field Descriptions
Bit Field
31-1 Reserved
0 IC
1506
M3 Inter-Integrated Circuit (I2C) Interface
Reserved
R-0
Value Description
Reserved
Masked Interrupt Status. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
0 An interrupt has not occurred or is masked.
1 An unmasked master interrupt was signaled and is pending.
Figure 22-22. I2C Master Interrupt Clear (I2CMICR) Register
Reserved
R-0
Value Description
Reserved
0 Interrupt Clear. Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in
the I2CMMIS register.
A read of this register returns no meaningful data.
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SPRUH22I – April 2012 – Revised November 2019
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1 0
MIS
R-0
1 0
IC
W-0