Introduction; Emac Block Diagram; Ethernet Mac - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com

19.1 Introduction

The EMAC module has the following features:
• Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant.
• Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
• Highly configurable
– Programmable MAC address
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
• IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets
• Efficient transfers using the Micro Direct Memory Access Controller (μDMA)
– Separate channels for transmit and receive
– Receive channel request asserted on packet receipt
– Transmit channel request asserted on empty transmit FIFO

19.2 EMAC Block Diagram

As shown in Figure
transmit and receive processing for Ethernet frames. It also provides the interface to the physical layer
(PHY) via an internal media independent interface (MII). The PHY layer communicates with the Ethernet
bus.
Microcontroller
ARM Cortex M3
Figure 19-2 shows more detail of the internal structure of the EMAC and how the register set relates to
various functions.
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
19-1, the MAC layer corresponds to the OSI model layer 2. The MAC layer provides
Figure 19-1. Ethernet MAC
Media
Access
Controller
MAC
(Layer 2)
Copyright © 2012–2019, Texas Instruments Incorporated
Physical
Layer
Magnetics
Entity
PHY
(Layer 1)
M3 Ethernet Media Access Controller (EMAC)
Introduction
RJ45
1381