Epi Host-Bus 8 Timing Extension (Epihb8Time), Offset 0X310; Epi Host-Bus 8 Timing Extension Register (Epihb8Time) [Offset 0X310]; Epi Host-Bus 8 Timing Extension Register (Epihb8Time) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 17-41. EPI Host-Bus 16 Configuration 4 Register (EPIHB16CFG4) Field Descriptions (continued)

17.11.29 EPI Host-Bus 8 Timing Extension (EPIHB8TIME), offset 0x310

NOTE: : The MODE field in the EPICFG register determines which configuration is enabled. For

EPIHB8TIME to be valid, the MODE field must be 0x2.

Figure 17-56. EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME) [offset 0x310]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-42. EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME) Field Descriptions

External Peripheral Interface (EPI)

CS3 Host Bus Sub-Mode

This field determines which Host Bus 16 sub-mode to use for CS3 in multiple chip-select mode.

Sub-mode use is determined by the connected external peripheral. See

on how this bit field affects the operation of the EPI signals.

Note: The CSBAUD bit must be set to enable this CS3 MODE field. If CSBAUD is clear, all chip

selects use the MODE configuration defined in the EPIHB16CFG register.

ADMUX – AD[15:0]

Data and Address are muxed.

ADNONMUX – D[15:0]

Data and address are separate. This mode is not practical in HB16 mode for normal peripherals

because there are generally not enough address bits available.

Continuous Read - D[15:0]

This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OE

strobing. This mode is not practical in HB16 mode for normal SRAMs because there are generally

not enough address bits available.

CS0 Input Ready Delay

Stall begins one EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock.

Stall begins two EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock

Stall begins three EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock.

CS0 Inter-transfer Capture Width

Controls the delay between Host-Bus transfers

SPRUH22I – April 2012 – Revised November 2019

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