Operating Modes; Initialization; Can Message Transfer (Normal Operation) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Three interface register sets control the CPU read and write accesses to the Message RAM. There are
two interface register sets for read and write access (IF1 and IF2) and one interface register set for read
access only (IF3). See also
message RAM.
In a dedicated test mode, the message RAM is memory-mapped and can be directly accessed.

23.2 Operating Modes

23.2.1 Initialization

The initialization mode is entered either by software (by setting the Init bit in the CAN_CTL register), by
hardware reset, or by going bus-off. While the Init bit is set, the message transfer from and to the CAN
bus is stopped, and the status of the CAN_TX output is recessive (high). The CAN error counters are not
updated. Setting the Init bit does not change any other configuration register.
To initialize the CAN Controller, the CPU has to configure the CAN bit timing and those message objects
which have to be used for CAN communication. Message objects which are not needed, can be
deactivated by with their MsgVal bits cleared.
The access to the Bit Timing register for the configuration of the bit timing is enabled when both Init and
CCE bits in the CAN Control register are set.
Clearing the Init bit finishes the software initialization. Afterwards the bit stream processor (BSP)
synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11
consecutive recessive bits (= Bus Idle) before it can take part in bus activities and start the message
transfer (for more details see
The initialization of the message objects is independent of the Init bit; however all message objects should
be configured to particular identifiers or set to "not valid" before the message transfer is started.
It is possible to change the configuration of message objects during normal operation by the CPU. After
setup and subsequent transfer of the message object from interface registers to the message RAM, the
acceptance filtering will be applied to it, when the modified message object number is same or smaller
than the previously found message object. This assures data consistency, even when changing message
objects, for example, while a pending CAN frame reception.

23.2.2 CAN Message Transfer (Normal Operation)

Once the CAN is initialized and the Init bit is reset to zero, the CAN Core synchronizes itself to the CAN
bus and is ready for communication.
Received messages are stored into their appropriate message objects if they pass acceptance filtering.
The whole message (MSGID, DLC, and up to eight data bytes) is stored into the message object. As a
consequence, when, for example, the identifier mask is used, the MSGID bits which are masked to "don't
care" may change in the message object when a received message is stored.
The CPU may read or write each message at any time via the Interface registers, as the message handler
guarantees data consistency in case of concurrent accesses.
Messages to be transmitted can be updated by the CPU. If a permanent message object (MSGID and
control bits set up during configuration and leaving unchanged for multiple CAN transfers) exists for the
message, it is possible to only update the data bytes. If several transmit messages should be assigned to
one message object, the whole message object has to be configured before the transmission of this
message is requested.
The transmission of multiple message objects may be requested at the same time. They are subsequently
transmitted, according to their internal priority. Messages may be updated or set to "not valid" at any time,
even if a requested transmission is still pending. However, the data bytes will be discarded if a message is
updated before a pending transmission has started.
Depending on the configuration of the message object, a transmission may be automatically requested by
the reception of a remote frame with a matching identifier.
SPRUH22I – April 2012 – Revised November 2019
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Section
23.13. The interface registers have the same word-length as the
Section
23.12).
Copyright © 2012–2019, Texas Instruments Incorporated
Operating Modes
M3 Controller Area Network (CAN)
1515

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