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Figure 16-28. DMA Channel Map Assignment (DMACHMAP0) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-35. DMA Channel Map Assignment (DMACHMAP0) Register Field Descriptions
Bit
Field
31-28
27-24
23-20
19-16
15-12
11-8
7-4
3-0
16.7.20 DMA Channel Map Assignment (DMACHMAP1) Register, offset 0x514
Each bit of the DMACHMAP0 register controls the channel assignments for the first, second, and third
mapping.
SPRUH22I – April 2012 – Revised November 2019
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Value
Description
0
Channel 7 First Assignment
1
Channel 7 Second Assignment
2
Channel 7 Third Assignment
3
Reserved
0
Channel 6 First Assignment
1
Channel 6 Second Assignment
2
Channel 6 Third Assignment
3
Reserved
0
Channel 5 First Assignment
1
Channel 5 Second Assignment
2
Channel 5 Third Assignment
3
Reserved
0
Channel 4 First Assignment
1
Channel 4 Second Assignment
2
Channel 4 Third Assignment
3
Reserved
0
Channel 3 First Assignment
1
Channel 3 Second Assignment
2
Channel 3 Third Assignment
3
Reserved
0
Channel 2 First Assignment
1
Channel 2 Second Assignment
2
Channel 2 Third Assignment
3
Reserved
0
Channel 1 First Assignment
1
Channel 1 Second Assignment
2
Channel 1 Third Assignment
3
Reserved
0
Channel 0 First Assignment
1
Channel 0 Second Assignment
2
Channel 0 Third Assignment
3
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
CHMAP0
R/W
M3 Micro Direct Memory Access ( µDMA)
µDMA Register Descriptions
0
1183
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