Synchronization On Late And Early Edges - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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If the magnitude of the phase error of the edge is less than or equal to the programmed value of SJW, the
results of hard synchronization and resynchronization are the same. If the magnitude of the phase error is
larger than SJW, the resynchronization cannot compensate the phase error completely, and an error of
(phase error - SJW) remains.
Only one synchronization may be done between two sample points. The synchronizations maintain a
minimum distance between edges and sample points, giving the bus level time to stabilize and filtering out
spikes that are shorter than (Prop_Seg + Phase_Seg1).
Apart from noise spikes, most synchronizations are caused by arbitration. All nodes synchronize "hard" on
the edge transmitted by the "leading" transceiver that started transmitting first, but due to propagation
delay times, they cannot become ideally synchronized. The "leading" transmitter does not necessarily win
the arbitration, therefore the receivers have to synchronize themselves to different transmitters that
subsequently "take the lead" and that are differently synchronized to the previously "leading" transmitter.
The same happens at the acknowledge field, where the transmitter and some of the receivers will have to
synchronize to that receiver that "takes the lead" in the transmission of the dominant acknowledge bit.
Synchronizations after the end of the arbitration will be caused by oscillator tolerance, when the
differences in the oscillator's clock periods of transmitter and receivers sum up during the time between
synchronizations (at most ten bits). These summarized differences may not be longer than the SJW,
limiting the oscillator's tolerance range.
The examples in Figure 23-13
errors. There are three drawings of each two consecutive bit timings. The upper drawing shows the
synchronization on a "late" edge, the lower drawing shows the synchronization on an "early" edge, and the
middle drawing is the reference without synchronization.
Rx-input
"normal"
edge
Rx-input
In the first example, an edge from recessive to dominant occurs at the end of Prop_Seg. The edge is
"late" since it occurs after the Sync_Seg. Reacting to the "late" edge, Phase_Seg1 is lengthened so that
the distance from the edge to the sample point is the same as it would have been from the Sync_Seg to
the sample point if no edge had occurred. The phase error of this "late" edge is less than SJW, so it is
fully compensated and the edge from dominant to recessive at the end of the bit, which is one nominal bit
time long, occurs in the Sync_Seg.
In the second example, an edge from recessive to dominant occurs during Phase_Seg2. The edge is
"early" since it occurs before a Sync_Seg. Reacting to the "early" edge, Phase_Seg2 is shortened and
Sync_Seg is omitted, so that the distance from the edge to the sample point is the same as it would have
been from a Sync_Seg to the sample point if no edge had occurred. As in the previous example, the
magnitude of this "early" edge's phase error is less than SJW, so it is fully compensated.
SPRUH22I – April 2012 – Revised November 2019
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show how the phase buffer segments are used to compensate for phase
Figure 23-13. Synchronization on Late and Early Edges
"late" edge
Sample-point
Sample-point
Sample-point
Sync_Seg
Prop_Seg
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Sample-point
Sample-point
"early" edge
Phase_Seg1
CAN Bit Timing
Recessive
dominant
Sample-point
Recessive
dominant
Phase_Seg2
M3 Controller Area Network (CAN)
1533