M3 Ram Configuration Registers Summary; M3 Ram Error Registers Summary - Texas Instruments Concerto F28M35 Series Technical Reference Manual

RAM Control Module Registers
5.2 RAM Control Module Registers
Register Acronym
CxDRCR1
CxSRCR1
MSxMSEL
MSxSRCR1
MSxSRCR2
MTOCMSGRCR
CxRTESTINIT1
MSxRTESTINIT1
MTOCRTESTINIT
CxRINITDONE1
MSxRINITDONE1
MTOCRINITDONE
Register Acronym
MCUNCWEADDR
MDUNCWEADDR
MCUNCREADDR
MDUNCREADDR
MCPUCREADDR
MDMACREADDR
MUEFLG
MUEFRC
MUECLR
MCECNTR
MCETRES
MCEFLG
MCEFRC
MCECLR
MCEIE
MNMAVFLG
MNMAVCLR
MMAVFLG
MMAVCLR
MNMWRAVADDR
434
Internal Memory
Table 5-5. M3 RAM Configuration Registers Summary
Size
(x8) Offset (x8) Protection
4 0x0 Protected
4 0x8 Protected
4 0x10 Protected +
Lock
4 0x20 Protected
4 0x24 Protected
4 0x30 Protected
4 0x40 Protected
4 0x50 Protected
4 0x60 Protected
4 0x70
4 0x78
4 0x88
Table 5-6. M3 RAM Error Registers Summary
Size
(x8) Offset (x8) Protection
4 0x0
4 0x4
4 0x8
4 0xC
4 0x10
4 0x14
4 0x20
4 0x24
4 0x28
4 0x2C
4 0x30
4 0x38
4 0x3C
4 0x40
4 0x44
4 0x50
4 0x58
4 0x60
4 0x68
4 0x70
Copyright © 2012–2019, Texas Instruments Incorporated
Reset Source Register Description
M3 Cx DEDRAM Configuration Register 1
M3 Cx SHRAM Configuration Register 1
Shared Sx SHRAM Master Select Register
M3 M3 Sx SHRAM Configuration Register 1
M3 M3 Sx SHRAM Configuration Register 2
M3 M3TOC28_MSG_RAM Configuration Register
M3 Cx RAM Test and Initialization Register 1
M3 M3 Sx RAM Test and Initialization Register 1
M3 MTOC_MSG_RAM Test and Initialization
Register
M3 Cx RAM INITDONE Register 1
M3 M3 Sx RAM INITDONE Register 1
M3 MTOC_MSG_RAM INITDONE Register 1
Reset Source Register Description
M3 M3 CPU Uncorrectable Write Error Address
Register
M3 M3 µDMA Uncorrectable Write Error Address
Register
M3 M3 CPU Uncorrectable Read Error Address
Register
M3 M3 µDMA Uncorrectable Read Error Address
Register
M3 M3 CPU Corrected Read Error Address
Register
M3 M3 µDMA Corrected Read Error Address
Register
M3 M3 Uncorrectable Error Flag Register
M3 M3 Uncorrectable Error Force Register
M3 M3 Uncorrectable Error Flag Clear Register
M3 M3 Corrected Error Counter Register
M3 M3 Corrected Error Threshold Register
M3 M3 Corrected Error Threshold Exceeded Flag
Register
M3 M3 Corrected Error Threshold Exceeded Force
Register
M3 M3 Corrected Error Threshold Exceeded Flag
Clear Register
M3 M3 Single Error Interrupt Enable Register
M3 Non-Master Access Violation Flag Register
M3 Non-Master Access Violation Flag Clear
Register
M3 Master Access Violation Flag Register
M3 Master Access Violation Flag Clear Register
M3 Non-Master CPU Write Access Violation
Address Register
SPRUH22I – April 2012 – Revised November 2019
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