Idle-Line Multiprocessor Communication Format - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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because, unlike the idle mode, it does not have to wait between blocks of data. However, at a high

transmit speed, the program is not fast enough to avoid a 10-bit idle in the transmission stream.

13.1.1.4.2 Controlling the SCI TX and RX Features

The multiprocessor mode is software selectable via the ADDR/IDLE MODE bit (SCICCR, bit 3). Both

modes use the TXWAKE flag bit (SCICTL1, bit 3), RXWAKE flag bit (SCIRXST, bit1), and the SLEEP flag

bit (SCICTL1, bit 2) to control the SCI transmitter and receiver features of these modes.

13.1.1.4.3 Receipt Sequence

In both multiprocessor modes, the receive sequence is:

1. At the receipt of an address block, the SCI port wakes up and requests an interrupt (bit number 1

RX/BK INT ENA-of SCICTL2 must be enabled to request an interrupt). It reads the first frame of the

block, which contains the destination address.

2. A software routine is entered through the interrupt and checks the incoming address. This address

byte is checked against its device address byte stored in memory.

3. If the check shows that the block is addressed to the device CPU, the CPU clears the SLEEP bit and

reads the rest of the block; if not, the software routine exits with the SLEEP bit still set and does not

receive interrupts until the next block start.

13.1.1.5 Idle-Line Multiprocessor Mode

In the idle-line multiprocessor protocol (ADDR/IDLE MODE bit=0), blocks are separated by having a

longer idle time between the blocks than between frames in the blocks. An idle time of ten or more high-

level bits after a frame indicates the start of a new block. The time of a single bit is calculated directly from

the baud value (bits per second). The idle-line multiprocessor communication format is shown in

(ADDR/IDLE MODE bit is bit 3 of SCICCR).

Figure 13-4. Idle-Line Multiprocessor Communication Format

(Pins SCIRXD, SCITXD)

Data format expanded

13.1.1.5.1 Idle-Line Mode Steps

The steps followed by the idle-line mode:

Step 1. SCI wakes up after receipt of the block-start signal.

Step 2. The processor recognizes the next SCI interrupt.

Step 3. The interrupt service routine compares the received address (sent by a remote transmitter) to

Step 4. If the CPU is being addressed, the service routine clears the SLEEP bit and receives the rest

of the data block.

Step 5. If the CPU is not being addressed, the SLEEP bit remains set. This lets the CPU continue to

execute its main program without being interrupted by the SCI port until the next detection of

SPRUH22I – April 2012 – Revised November 2019

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First frame within block

Is address; it follows idle

period of 10 bits or more

Several blocks of frames

Idle periods of 10 bits or more

separate the blocks

One block of frames

Frame within

less than 10

C28 Serial Communications Interface (SCI)

Enhanced SCI Module Overview

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