Program Status Register (Psr); Psr Register Combinations; Program Status Register (Psr) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Programming Model
These registers can be accessed individually or as a combination of any two or all three registers, using
the register name as an argument to the MSR or MRS instructions. For example, all of the registers can
be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR
instruction. Table 24-7
instruction descriptions in the Cortex-M3 Instruction Set Technical User's Manualfor more information
about how to access the program status registers.
Register
PSR
IEPSR
IAPSR
EAPSR
(1)
The processor ignores writes to the IPSR bits.
(2)
Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
31 30
N Z
R/W-0 R/W-0
23
15
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31 N
30 Z
29 C
28 V
1574
Cortex-M3 Processor
shows the possible register combinations for the PSR. See the MRS and MSR
Table 24-7. PSR Register Combinations
Figure 24-7. Program Status Register (PSR)
29 28
C V
R/W-0 R/W-0
ICI/IT
R/O-0x00
Table 24-8. Program Status Register (PSR) Field Descriptions
Value Description
APSR Negative or Less Flag
0 The previous operation result was positive, zero, greater than, or equal
1 The previous operation result was negative or less than.
APSR Zero Flag
0 The previous operation result was non-zero.
1 The previous operation result was zero
APSR Carry or Borrow Flag
0 The previous add operation did not result in a carry bit or the previous subtract operation resulted in
a borrow bit.
1 The previous add operation resulted in a carry bit or the previous subtract operation did not result in
a borrow bit.
The value of this bit is only meaningful when accessing PSR or APSR.
APSR Overflow Flag
0 The previous operation did not result in an overflow
1 The previous operation resulted in an overflow.
The value of this bit is only meaningful when accessing PSR or APSR.
Copyright © 2012–2019, Texas Instruments Incorporated
Type
(1) (2)
R/W
RO
R/W
R/W
27 26
Q
R/W-0
Reserved
R-0
10
ISRNUM
R/0-0x00
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Combination
APSR, EPSR, and IPSR
EPSR and IPSR
APSR and IPSR
APSR and EPSR
25 24
ICI / IT THUMB
R/0-0x0 R/0-1
16
9 8
Reserved
R-0
0
Submit Documentation Feedback