Cx Ram Test And Initialization Register 1 (Cxrtestinit1); Cx Ram Test And Initialization Register 1 (Cxrtestinit1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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5.2.1.7

Cx RAM Test and Initialization Register 1 (CxRTESTINIT1)

Figure 5-10. Cx RAM Test and Initialization Register 1 (CxRTESTINIT1)
31
7 6
ECCPARTEST RAMINITC3
C3
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-15. Cx RAM Test and Initialization Register 1 (CxRTESTINIT1) Field Descriptions
Bit Field
31-8 Reserved
7 ECCPARTESTC3
6 RAMINITC3
5 ECCPARTESTC2
4 RAMINITC2
3 ECCPARTESTC1
2 RAMINITC1
1 ECCPARTESTC0
0 RAMINITC0
SPRUH22I – April 2012 – Revised November 2019
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5 4
ECCPARTEST RAMINITC2
C2
R/W-0 R/W-0
Value Description
Reserved
Enable/Disable RAMTEST Feature for C3 RAM Block.
0 RAMTEST feature is disabled for C3 RAM block.
1 RAMTEST feature is enabled for C3 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization C3. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of C3 RAM block with data 0x0 and corresponding data an address
ECC/parity bits.
Enable/Disable RAMTEST Feature for C2 RAM Block
0 RAMTEST feature is disabled for C2 RAM block.
1 RAMTEST feature is enabled for C2 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization C2. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of C2 RAM block with data 0x0 and corresponding data an address
ECC/parity bits.
Enable/Disable RAMTEST Feature for C1 RAM Block
0 RAMTEST feature is disabled for C1 RAM block.
1 RAMTEST feature is enabled for C1 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization C1. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of C1 RAM block with data 0x0 and corresponding data an address
ECC/parity bits.
Enable/Disable RAMTEST Feature for C0 RAM Block
0 RAMTEST feature is disabled for C0 RAM block.
1 RAMTEST feature is enabled for C0 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization C0. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of C0 RAM block with data 0x0 and corresponding data an address
ECC/parity bits.
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Reserved
R-0
3 2
ECCPARTEST RAMINITC1
C1
R/W-0 R/W-0
RAM Control Module Registers
8
1 0
ECCPARTEST RAMINITC0
C0
R/W-0 R/W-0
Internal Memory
445