Bus Interface Speed; Non-Blocking Read Cycle; Normal Read Cycle; Sdram Non-Blocking Read Cycle - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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The default value in the RFSH field is 750 decimal or 0x2EE to allow for a margin of safety and providing
15 µs per refresh. It is important to note that this number should always be smaller or equal to what is
required by the above equation. For example, if running the external clock at 25 MHz (40 ns per clock
period), 390 is the highest number that may be used. Note that the external clock may be 25 MHz when
the system clock is 25 MHz or when the system clock is 50 MHz and configuring the COUNT0 field in the
EPIBAUD register to 1 (divide by 2).
If a number larger than allowed is used, the SDRAM is not refreshed often enough, and data is lost.

17.6.3 Bus Interface Speed

The EPI Controller SDRAM interface can operate up to 62.5 MHz. The COUNT0 field in the EPIBAUD
register configures the speed of the EPI clock. For system clock (SYSCLK) speeds up to 62.5 MHz, the
COUNT0 field can be 0x0000, and the SDRAM interface can run at the same speed as SYSCLK.
However, if SYSCLK is running at higher speeds, the bus interface can run only as fast as half speed, and
the COUNT0 field must be configured to at least 0x0001.

17.6.4 Non-Blocking Read Cycle

Figure 17-2 shows a non-blocking read cycle of n halfwords; n can be any number greater than or equal to
1. The cycle begins with the Activate command and the row address on the EPI0S[15:0] signals. With the
programmed CAS latency of 2, the Read command with the column address on the EPI0S[15:0] signals
follows after 2 clock cycles. Following one more NOP cycle, data is read in on the EPI0S[15:0] signals on
every rising clock edge. The Burst Terminate command is issued during the cycle when the next-to-last
halfword is read in. The DQMH and DQML signals are deasserted after the last halfword of data is
received; the CS signal deasserts on the following clock cycle, signaling the end of the read cycle. At least
one clock period of inactivity separates any two SDRAM cycles..
CLK
(EPI0S31)
CKE
(EPI0S30)
CS
(EPI0S29)
WE
(EPI0S28)
RAS
(EPI0S19)
CAS
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
Row
(EPI0S [15:0])
Activate
AD [15:0]drivenout

17.6.5 Normal Read Cycle

Figure 17-3 shows a normal read cycle of n halfwords; n can be 1 or 2. The cycle begins with the Activate
command and the row address on the EPI0S[15:0] signals. With the programmed CAS latency of 2, the
Read command with the column address on the EPI0S[15:0] signals follows after two clock cycles.
Following one more NOP cycle, data is read in on the EPI0S[15:0] signals on every rising clock edge. The
DQMH, DQML, and CS signals are deasserted after the last halfword of data is received, signaling the
end of the cycle. At least one clock period of inactivity separates any two SDRAM cycles.
SPRUH22I – April 2012 – Revised November 2019
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Figure 17-2. SDRAM Non-Blocking Read Cycle
Column
NOP NOP Read
AD [15:0]drivenout
Copyright © 2012–2019, Texas Instruments Incorporated
Data 0 Data 1
NOP
AD [15:0]drivenin
External Peripheral Interface (EPI)
SDRAM Mode
... Data n
Burst
Term
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