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All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
generates a single interrupt request to the controller regardless of the number of active interrupts. Each of
the four individual maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt
Mask (SSIIM) register. Setting the appropriate mask bit enables the interrupt.
The individual outputs, along with a combined interrupt output, allow use of either a global interrupt service
routine or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow
interrupts have been separated from the status interrupts so that data can be read or written in response
to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw
Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers.
The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is
currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is
emptied before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the
Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing a 1 to the RTIC bit in the
SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared so late that the ISR returns
before the interrupt is actually cleared, or the ISR may be re-activated unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This
interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In
addition, because transmitted data and received data complete at exactly the same time, the interrupt can
also indicate that read data is ready immediately, without waiting for the receive FIFO time-out period to
complete.
20.3.4 Frame Formats
Each data frame is between 4- and 16-bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. Two basic frame types can be selected:
•
Texas Instruments synchronous serial
•
Freescale SPI
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions
at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk
is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after
a timeout period.
For Freescale SPI frame format, the serial frame (SSIFss) pin is active low, and is asserted (pulled down)
during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock
period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the
SSI and the off-chip slave device drive their output data on the rising edge of SSIClk and latch data from
the other device on the falling edge.
The figure below shows the Texas Instruments synchronous serial frame format for a single transmitted
frame.
Figure 20-2. TI Synchronous Serial Frame Format (Single Transfer)
In this mode, SSIClk and SSIFss are forced low, and the transmit data line SSITx is tristated whenever the
SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed high for one
SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift
register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4- to 16-bit data frame is
shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the
off-chip serial slave device.
SPRUH22I – April 2012 – Revised November 2019
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SSIClk
SSIFss
SSITx/SSIRx
MSB
Copyright © 2012–2019, Texas Instruments Incorporated
LSB
4 to16 bits
M3 Synchronous Serial Interface (SSI)
Functional Description
1413
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