Clocking And Framing Data; Clocking; Serial Words; Two Methods By Which The Mcbsp Can Compand Internal Data - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Clocking and Framing Data

• The McBSP is enabled in digital loopback mode with companding appropriately enabled by
RCOMPAND and XCOMPAND. Receive and transmit interrupts (RINT when RINTM = 0 and XINT
when XINTM = 0) or synchronization events (REVT and XEVT) allow synchronization of the CPU or
DMA to these conversions, respectively. Here, the time for this companding depends on the serial bit
rate selected.
Figure 15-6. Two Methods by Which the McBSP Can Compand Internal Data
RSR1
DR
(2) (DLB)
DX
15.1.5.3 Reversing Bit Order: Option to Transfer LSB First
Generally, the McBSP transmits or receives all data with the most significant bit (MSB) first. However,
certain 8-bit data protocols (that do not use companded data) require the least significant bit (LSB) to be
transferred first. If you set XCOMPAND = 01b in XCR2, the bit ordering of 8-bit words is reversed (LSB
first) before being sent from the serial port. If you set RCOMPAND = 01b in RCR2, the bit ordering of 8-bit
words is reversed during reception. Similar to companding, this feature is enabled only if the appropriate
word length bits are set to 0, indicating that 8-bit words are to be transferred serially. If either phase of the
frame does not have an 8-bit word length, the McBSP assumes the word length is eight bits, and LSB-first
ordering is done.
15.2 Clocking and Framing Data
This section explains basic concepts and terminology important for understanding how McBSP data
transfers are timed and delimited.

15.2.1 Clocking

Data is shifted one bit at a time from the DR pin to the RSR(s) or from the XSR(s) to the DX pin. The time
for each bit transfer is controlled by the rising or falling edge of a clock signal.
The receive clock signal (CLKR) controls bit transfers from the DR pin to the RSR(s). The transmit clock
signal (CLKX) controls bit transfers from the XSR(s) to the DX pin. CLKR or CLKX can be derived from a
pin at the boundary of the McBSP or derived from inside the McBSP. The polarities of CLKR and CLKX
are programmable.
In the example in Figure
Figure 15-7. Example - Clock Signal Control of Bit Transfer Timing
Internal
CLK(R/X)
Internal
FS(R/X)
A1
D(R/X)
NOTE: The McBSP cannot operate at a frequency faster than ½ the LSPCLK frequency. When
driving CLKX or CLKR at the pin, choose an appropriate input clock frequency. When using
the internal sample rate generator for CLKX and/or CLKR, choose an appropriate input clock
frequency and divide down value (CLKDV) (i.e., be certain that CLKX or CLKR ≤ LSPCLK/2).

15.2.2 Serial Words

Bits traveling between a shift register (RSR or XSR) and a data pin (DR or DX) are transferred in a group
called a serial word. You can define how many bits are in a word.
1042
C28 Multichannel Buffered Serial Port (McBSP)
RBR1
Expand
(1)
Compress
XSR1
15-7, the clock signal controls the timing of each bit transfer on the pin.
A0 B7 B6
Copyright © 2012–2019, Texas Instruments Incorporated
DRR1
To CPU or DMA controller
DXR1
From CPU or DMA controller
B5 B4 B3 B2 B1
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
B0
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