Usb Interrupt Enable Register (Usbie), Offset 0X00B; Usb Interrupt Enable Register (Usbie) In Otg A/Host Mode; Usb Interrupt Enable Register (Usbie) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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18.5.8 USB Interrupt Enable Register (USBIE), offset 0x00B

NOTE: Use caution when reading this register. Performing a read may change bit status.
The USB interrupt enable 8-bit register (USBIE) provides interrupt enable bits for each of the interrupts in
USBIS. At reset interrupts 1 and 2 are enabled in Device mode.
Mode(s): OTG A or Host
USBIE in OTG A/Host Mode is shown in
Figure 18-11. USB Interrupt Enable Register (USBIE) in OTG A/Host Mode
7 6
VBUSERR SESREQ
R-W R-W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-14. USB Interrupt Enable Register (USBIE) in OTG A/Host Mode Field Descriptions
Bit Field
7 VBUSERR
6 SESREQ
5 DISCON
4 CONN
3 SOF
2 BABBLE
1 RESUME
0 Reserved
SPRUH22I – April 2012 – Revised November 2019
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OTG B or Device
Figure 18-11
5 4
DISCON CONN
R-W R-W
Value Description
Enable VBUS Error Interrupt
0 The VBUSERR interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the VBUSERR bit in the USBIS register is set.
Enable Session Request
0 The SESREQ interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the SESREEQ bit in the USBIS register is set.
Enable Disconnect Interrupt
0 The DISCON interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set.
Enable Connect Interrupt
0 The CONN interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the CONN bit in the USBIS register is set.
Start of Frame
0 The SOF interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set.
Babble Detected
0 The BABBLE interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the BABBLE bit in the USBIS register is set.
RESUME Signaling Detected. This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC
registers should be used.
0 The RESUME interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set.
0 Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
and described in Table 18-14.
3 2
SOF BABBLE
R-W R-W
M3 Universal Serial Bus (USB) Controller
Register Descriptions
1 0
RESUME Reserved
R-W R-0
1313