Missing Clock Detection Logic - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Safety Features
Note: The missing clock circuit is not active during the PLL 1024 cycle lock time. To avoid missing clock
detection, the user should extend the external reset (XRS) so it covers appropriate lock time.
Figure 1-10 shows the missing clock logic functional flow.
1. Power up
missing clock
detection
condition
2. Missing clock
logic enabled at
XRSn reset
1. H/W Clears 3 bit 10 MHz CLK Counter
2. H/W Clears 8 bit OSCCLK ref. clock
counter
3. Both counters start counting again
Ref clock high limit >=
counter >= Ref clock
122
System Control and Interrupts
Figure 1-10. Missing Clock Detection Logic
1. Software programs refclk limit registers
2. Missing Clock logic enabled by default
and re-enabled if missing clock status is
cleared
No
Missing
clock circuit
enabled
Yes
No
10MHz CLK
counter
overflow?
Yes
Logic reads
OSCCLK re.
clock counter
value
OSCCLK ref.clock
No
low limit
Yes
Copyright © 2012–2019, Texas Instruments Incorporated
Disable
missing clock
circuit
1. system PLL bypassed
CLOCKFAIL
2. Clock to device = 10MHz Internal
condition
Oscillator.CLK
generated
3. Disable missing clock counters
4. C28 side PWMs tripped based on
configuration
1. Generate NMI to M3 and C28 CPU
2. Start both NMIWD counters
SPRUH22I – April 2012 – Revised November 2019
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