Usb Transmit Control And Status Endpoint N Low Register (Usbtxcsrl[1]- Usbtxcsrl[15]); Usb Transmit Control And Status Endpoint N Low Register (Usbtxcsrl[N]) In Otg A/Host Mode; Usb Transmit Control And Status Endpoint N Low Register (Usbtxcsrl[N]) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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18.5.34 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-
USBTXCSRL[15])
The USB transmit control and status endpoint n low 8-bit registers (USBTXCSRL[n]) provide control and
status bits for transfers through the currently selected transmit endpoint.
For the specific offset for each register see
Mode(s): OTG A or Host
The USBTXCSRL[n] registers in OTG A/Host Mode are shown in
44.
Figure 18-41. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in OTG
7 6
NAKTO CLRDT
R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-44. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
Bit Field Value
7 NAKTO
0
1
6 CLRDT
0
1
5 STALLED
0
1
4 SETUP
0
1
3 FLUSH
0
1
2 ERROR
0
1
1 FIFONE
0
1
SPRUH22I – April 2012 – Revised November 2019
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Table
OTG B or Device
A/Host Mode
5 4
STALLED SETUP
R/W-0 R/W-0
in OTG A/Host Mode Field Descriptions
Description
NAK Timeout. Software must clear this bit to allow the endpoint to continue.
No timeout
Bulk endpoints only: Indicates that the transmit endpoint is halted following the receipt of NAK
responses for longer than the time set by the NAKLMT field in the USBTXINTERVAL[n] register.
Clear DataToggle
No effect
Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register.
Endpoint Stalled. Software must clear this bit.
A STALL handshake has not been received
Indicates that a STALL handshake has been received. When this bit is set, any μDMA request that is in
progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared.
Setup Packet.
No SETUP token is sent.
Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same
time as the TXRDY bit is set.
Note: Setting this bit also clears the DT bit in the USBTXCSRH[n] register.
Flush FIFO. This bit can be set simultaneously with the TXRDY bit to abort the packet that is currently
being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice
to completely clear the FIFO.
No effect
Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit
is cleared. The EPn bit in the USBTXIS register is also set in this situation.
Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be
corrupted.
Error. Software must clear this bit.
No error
Three attempts have been made to send a packet and no handshake packet has been received. The
TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed in
this situation.
Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode.
FIFO Not Empty
The FIFO is empty
At least one packet is in the transmit FIFO.
Copyright © 2012–2019, Texas Instruments Incorporated
18-4.
Figure 18-41
3 2
FLUSH ERROR
R/W-0 R/W-0
M3 Universal Serial Bus (USB) Controller
Register Descriptions
and described in Table 18-
1 0
FIFONE TXRDY
R/W-0 R/W-0
1339