Transfer Modes; Control Structure Memory Map; Channel Control Structure - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description
Table 16-4 shows an individual control structure entry in the control table. Each entry is aligned on a 16-
byte boundary. The entry contains four long words: the source end pointer, the destination end pointer, the
control word, and an unused entry. The end pointers point to the ending address of the transfer and are
inclusive. If the source or destination is non-incrementing (as for a peripheral register), then the pointer
should point to the transfer address.
The control word contains the following fields:
• Source and destination data sizes
• Source and destination address increment size
• Number of transfers before bus arbitration
• Total number of items to transfer
• Useburst flag
• Transfer mode
The control word and each field are described in detail in
transfer size and transfer mode fields as the transfer is performed. At the end of a transfer, the transfer
size indicates 0, and the transfer mode indicates "stopped." Because the control word is modified by the
µDMA controller, it must be reconfigured before each new transfer. The source and destination end
pointers are not modified, so they can be left unchanged if the source or destination addresses remain the
same.
Prior to starting a transfer, a µDMA channel must be enabled by setting the appropriate bit in the DMA
Channel Enable Set (DMAENASET) register. A channel can be disabled by setting the channel bit in the
DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete µDMA transfer, the
controller automatically disables the channel.

16.3.6 Transfer Modes

The µDMA controller supports several transfer modes. Two of the modes support simple one-time
transfers. Several complex modes support a continuous flow of data.
16.3.6.1 Stop Mode
While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word. When
the mode field has this value, the µDMA controller does not perform any transfers and disables the
channel if it is enabled. At the end of a transfer, the µDMA controller updates the control word to set the
mode to Stop.
1154
M3 Micro Direct Memory Access ( µDMA)
Table 16-3. Control Structure Memory Map
Offset
0x0
0x10
...
0x1F0
0x200
0x210
...
0x3F0
Table 16-4. Channel Control Structure
Offset
0x000
0x004
0x008
0x00C
Copyright © 2012–2019, Texas Instruments Incorporated
Channel
0, Primary
1, Primary
...
31, Primary
0, Alternate
1, Alternate
...
31, Alternate
Description
Source End Pointer
Destination End Pointer
Control Word
Unused
Section 16.6. The µDMA controller updates the
SPRUH22I – April 2012 – Revised November 2019
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