Register Descriptions; Gpio Data (Gpiodata) Register; Gpio Data (Gpiodata) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
0xFEC
0xFF0
0xFF4
0xFF8
0xFFC

4.1.6 Register Descriptions

The remainder of this section lists and describes the GPIO registers, in numerical order by address offset.
4.1.6.1 GPIO Data (GPIODATA) Register, offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the GPIODATA
register are transferred onto the GPIO port pins if the respective pins have been configured as outputs
through the GPIO Direction (GPIODIR) register .
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits
[9:2], must be set. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from the
address used to access the data register, bits [9:2]. Bits that are set in the address mask cause the
corresponding bits in GPIODATA to be read, and bits that are clear in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs,
or it returns the value on the corresponding input pin when these are configured as inputs. All bits are
cleared by a reset.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-8 Reserved
7-0 DATA
348
General-Purpose Input/Output (GPIO)
Table 4-5. GPIO Register Map (continued)
GPIOPeriphID3 RO
GPIOPCellID0 RO
GPIOPCellID1 RO
GPIOPCellID2 RO
GPIOPCellID3 RO
Figure 4-4. GPIO Data (GPIODATA) Register
R-0
Table 4-6. GPIO Data (GPIODATA) Register Field Descriptions
Value Description
Reserved
00h GPIO Data
This register is virtually mapped to 256 locations in the address space. To facilitate the reading and
writing of data to these registers by independent drivers, the data read from and written to the
registers are masked by the eight address lines [9:2]. Reads from this register return its current
state. Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured
as outputs.
See Section 4.1.3.2.2 for examples of reads and writes.
Copyright © 2012–2019, Texas Instruments Incorporated
0x0000.0001
0x0000.000D
0x0000.00F0
0x0000.0005
0x0000.00B1
Reserved
R-0
8 7
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
GPIO Peripheral
Identification 3
GPIO PrimeCell
Identification 0
GPIO PrimeCell
Identification 1
GPIO PrimeCell
Identification 2
GPIO PrimeCell
Identification 3
DATA
R/W-0
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