Pie, Intx Group Enable Register (Pieierx) (X = 1 To 12); Pie, Acknowledge (Pieack) Register Field Descriptions; Pie, Intx Group Enable Register (Pieierx) (X = 1 To 12) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Registers
Table 1-82. PIE, Acknowledge (PIEACK) Register Field Descriptions
Bits Field
15-12 Reserved
11-0 PIEACK
(1)
bit x = PIEACK bit 0 - PIEACK bit 11. Bit 0 refers to CPU INT1 up to Bit 11, which refers to CPU INT12
1.13.5.13.3 PIE Interrupt Enable Registers
There are twelve PIEIER registers, one for each CPU interrupt used by the PIE module (INT1-INT12).
Figure 1-72. PIE, INTx Group Enable Register (PIEIERx) (x = 1 to 12)
15
7 6
INTx.8 INTx.7
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-83. PIE, INTx Group Enable Register (PIEIERx) (x = 1 to 12) Field Descriptions
Bits Field Description
15-8 Reserved Reserved
7 INTx.8 These register bits individually enable an interrupt within a group and behave very much like the core interrupt
enable register. Setting a bit to 1 enables the servicing of the respective interrupt. Setting a bit to 0 disables
6 INTx.7
the servicing of the interrupt. x = 1 to 12. INTx means CPU INT1 to INT12
5 INTx.6
4 INTx.5
3 INTx.4
2 INTx.3
1 INTx.2
0 INTx.1
NOTE: Care must be taken when clearing PIEIER bits during normal operation. See Section
Section 1.5.4.3.2
208
System Control and Interrupts
Value Description
Reserved
Each bit in PIEACK refers to a specific PIE group. Bit 0 refers to interrupts in PIE group 1 that
are MUXed into INT1 up to Bit 11, which refers to PIE group 12 which is MUXed into CPU
INT12.
(1)
bit x = 0 If a bit reads as a 0, it indicates that the PIE can send an interrupt from the respective group to
the CPU.
Writes of 0 are ignored.
bit x = 1 Reading a 1 indicates if an interrupt from the respective group has been sent to the CPU and all
other interrupts from the group are currently blocked.
Writing a 1 to the respective interrupt bit clears the bit and enables the PIE block to drive a
pulse into the CPU interrupt input if an interrupt is pending for that group.
5 4
INTx.6 INTx.5
R/W-0 R/W-0
for the proper procedure for handling these bits.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
INTx.4 INTx.3
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
8
1 0
INTx.2 INTx.1
R/W-0 R/W-0
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