Message Interface Register Sets 1 And 2 - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Message Interface Register Sets
Due to the structure of the Message RAM, it is not possible to change single bits or bytes of a message
object. Instead, always a complete message object in the Message RAM is accessed. Therefore, the data
transfer from the IF1 or IF2 registers to the Message RAM requires the message handler to perform a
read-modify-write cycle: first those parts of the message object that are not to be changed are read from
the Message RAM into the Interface Register Set, and after the update, the whole content of the Interface
Register Set is written into the message object.
After the partial write of a message object, those parts of the Interface register set which are not selected
in the Command register, will be set to the actual contents of the selected message object. After the
partial read of a message object, those parts of the Interface Register Set which are not selected in the
Command register, will be left unchanged.
By buffering the data to be transferred, the Interface Register sets avoid conflicts between concurrent
CPU accesses to the Message RAM and CAN message reception and transmission. A complete message
object (see Section
RAM and the IF1 or IF2 register set (see
in parallel on all selected parts of the message object, guarantees the data consistency of the CAN
message.
That being said, there is one condition that can cause a write access to the message RAM to be lost. If
MsgVal = 1 for the message object which is accessed and CAN communication is ongoing, a transfer from
the IFx register to message RAM may be lost. The reason for this is that it might happen that the IFx
register write to the message RAM occurs in between a read-modify-write access of the Host Message
Handler when it is in the process of receiving a message for the same message object.
To avoid this issue with receive mail boxes, reset MsgVal before changing any of the following: Id28-0,
Xtd, Dir, DLC3-0, RxIE, TxIE, RmtEn, EoB, Umask, Msk28-0, MXtd, and MDir.
To avoid this issue with transmit mail boxes, reset MsgVal before changing any of the following: Dir, RxIE,
TxIE, RmtEn, EoB, Umask, Msk28-0, MXtd, and MDir. Other fields not listed above, like Data, may be
changed without fear of losing a write to the message RAM.

23.13.1 Message Interface Register Sets 1 and 2

The IF1 and IF2 register sets control the data transfer to and from the message object. The Command
register addresses the desired message object in the Message RAM and specifies whether a complete
message object or only parts should be transferred. The data transfer is initiated by writing the message
number to the bits [7:0] of the Command register.
When the CPU initiates a data transfer between the IF1 or IF2 registers and Message RAM, the message
handler sets the Busy bit in the respective Command register to '1'. After the transfer has completed, the
Busy bit is set back to '0' (see
1538
M3 Controller Area Network (CAN)
23.14.1) or parts of the message object may be transferred between the Message
Section
Figure 23-16 ).
Copyright © 2012–2019, Texas Instruments Incorporated
23.15.15) in one single transfer. This transfer, performed
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Submit Documentation Feedback