Control Subsystem Clocking - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Clock Control
NOTE:
[1] In deep sleep mode, if the application wants to wake up using the CAN or USB modules
as configured by the respective DSCGC register bits, it is possible to do so. But the USB
PLL is turned off, since generation of the wake up signal from the USB controller does not
need a proper clock.
[2] The deep sleep clock as configured by the DSLPCLKCFG register, followed by the
M3SSDIVSEL register, becomes the M3_SS_CLK input to the CANBCLKSEL logic. Software
can decide to use either of the same three clock sources to the CAN bit clock as decided by
the CANBCLKSEL register configuration.
[3] Below describes which clock will drive which peripherals in deep sleep mode:
For M3 peripherals in deep sleep mode, the clock will be divided by the deep-sleep
divider followed by the M3_SS divider.
For C28 peripherals in deep sleep mode, the clock will be divided by the deep sleep
divider only.

1.8.4 Control Subsystem Clocking

The input clock to the C28x processor is the C28CLKIN, (refer to
PLLSYSCLK coming from the master subsystem when clocking to the control subsystem is enabled (refer
to the CCLKOFF register for more details). As mentioned previously, PLLSYSCLK is either derived from
the output of the PLL (when the PLL is enabled and locked) or from the MAIN OSCCLK directly (when the
PLL is bypassed or turned off), divided by the SYSDIVSEL divider.
The control subsystem, by default after a reset, will not be able to configure the PLL and SYSDIVSEL
registers. The PLL and SYSDIVSEL configuration is read-only for the control subsystem while the master
subsystem can configure them as needed. To enable the ability to configure clocking from the control
subsystem, there is a provision provided where the control subsystem can claim the ownership of clocking
control and configure the PLL and SYSDIVSEL as needed.
The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The control subsystem operates
in one of three modes: normal mode, idle mode, or standby mode.
Figure 1-12
shows the clocking control on the control subsystem.
130
System Control and Interrupts
Copyright © 2012–2019, Texas Instruments Incorporated
Figure
1-12) which is the same as
SPRUH22I – April 2012 – Revised November 2019
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