Time-Base Status Register (Tbsts); High-Resolution Period Control Register (Hrpctl); Time-Base Status Register (Tbsts) Field Descriptions; High-Resolution Period Control Register (Hrpctl) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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LEGEND: R/W = Read/Write; R = Read only; R/W1C = Read/Write 1 to clear; -n = value after reset

Table 7-33. Time-Base Status Register (TBSTS) Field Descriptions

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7-34. High-Resolution Period Control Register (HRPCTL) Field Descriptions

This register is EALLOW protected.

This register is used with Type 1 ePWM modules (support high-resolution period) only.

C28 Enhanced Pulse Width Modulator (ePWM) Module

Figure 7-83. Time-Base Status Register (TBSTS)

Time-Base Counter Max Latched Status Bit

Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will

have no effect.

Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing

a 1 to this bit will clear the latched event.

Input Synchronization Latched Status Bit

Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has

Reading a 1 on this bit indicates that an external synchronization event has occurred

(EPWMxSYNCI). Writing a 1 to this bit will clear the latched event.

Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no

meaning. To make this bit meaningful, you must first set the appropriate mode via

TBCTL[CTRMODE].

Time-Base Counter is currently counting down.

Time-Base Counter is currently counting up.

Figure 7-84. High-Resolution Period Control Register (HRPCTL)

SPRUH22I – April 2012 – Revised November 2019

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