Uart Fractional Baud-Rate Divisor Register (Uartfbrd), Offset 0X028; Uart Line Control Register (Uartlcrh), Offset 0X02C; Uart Fractional Baud-Rate Divisor Register (Uartfbrd); Uart Line Control Register (Uartlcrh) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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21.7.6 UART Fractional Baud-Rate Divisor Register (UARTFBRD), offset 0x028

The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on

reset. When changing the UARTFBRD register, the new value does not take effect until

transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be

followed by a write to the UARTLCRH register. See

Figure 21-13. UART Fractional Baud-Rate Divisor Register (UARTFBRD)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-8. UART Fractional Baud-Rate Divisor (UARTFBRD) Register Field Descriptions

The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and

stop bit selection are implemented in this register.

When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also

be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-9. UART Line Control Register (UARTLCRH) Field Descriptions

SPRUH22I – April 2012 – Revised November 2019

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Fractional Baud-Rate Divisor

Figure 21-14. UART Line Control Register (UARTLCRH)

UART Stick Parity Select

When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When

bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1.When this bit

is cleared, stick parity is disabled.

UART Word Length

The bits indicate the number of data bits transmitted or received in a frame as follows:

5 bits (default)

UART Enable FIFOs

The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.

The transmit and receive FIFObuffers are enabled (FIFOmode).

Section 21.3.2

for configuration details.

M3 Universal Asynchronous Receivers/Transmitters (UARTs)

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