Table of Contents
Advertisement
www.ti.com
20.5.2.6 SSIIM Register (Offset = 14h) [reset = 0h]
SSIIM is shown in
Return to the
Summary
SSI Interrupt Mask
31
30
23
22
15
14
7
6
RESERVED
EOTIM
R-0h
R/W-0h
Bit
Field
31-7
RESERVED
6
EOTIM
5
DMATXIM
4
DMARXIM
3
TXIM
2
RXIM
1
RTIM
0
RORIM
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Figure 20-15
and described in
Table.
Figure 20-15. SSIIM Register
29
28
21
20
13
12
5
4
DMATXIM
DMARXIM
R/W-0h
R/W-0h
Table 20-9. SSIIM Register Field Descriptions
Type
Reset
R
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
Copyright © 2012–2019, Texas Instruments Incorporated
Table
20-9.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
TXIM
RXIM
R/W-0h
R/W-0h
Description
Reserved
End of Transmit Interrupt Mask
Value Description
0 The end of transmit interrupt is masked.
1 The end of transmit interrupt is not masked.
Reset type: PER.RESET
SSI Transmit DMA Interrupt Mask
Value Description
0 The transmit DMA interrupt is masked.
1 The transmit DMA interrupt is not masked.
Reset type: PER.RESET
SSI Receive DMA Interrupt Mask
Value Description
0 The receive DMA interrupt is masked.
1 The receive DMA interrupt is not masked.
Reset type: PER.RESET
SSI Transmit FIFO Interrupt Mask
Value Description
0 The transmit FIFO interrupt is masked.
1 The transmit FIFO interrupt is not masked.
Reset type: PER.RESET
SSI Receive FIFO Interrupt Mask
Value Description
0 The receive FIFO interrupt is masked.
1 The receive FIFO interrupt is not masked.
Reset type: PER.RESET
SSI Receive Time-Out Interrupt Mask
Value Description
0 The receive FIFO time-out interrupt is masked.
1 The receive FIFO time-out interrupt is not masked.
Reset type: PER.RESET
SSI Receive Overrun Interrupt Mask
Value Description
0 The receive FIFO overrun interrupt is masked.
1 The receive FIFO overrun interrupt is not masked.
Reset type: PER.RESET
M3 Synchronous Serial Interface (SSI)
SSI Registers
26
25
18
17
10
9
2
1
RTIM
R/W-0h
24
16
8
0
RORIM
R/W-0h
1429
Advertisement
Chapters
Table of Contents
