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I2C Module Operational Details
14.2.7 Clock Synchronization
Under normal conditions, only one master device generates the clock signal, SCL. During the arbitration
procedure, however, there are two or more masters and the clock must be synchronized so that the data
output can be compared.
SCL means that a device that first generates a low period on SCL overrules the other devices. At this
high-to-low transition, the clock generators of the other devices are forced to start their own low period.
The SCL is held low by the device with the longest low period. The other devices that finish their low
periods must wait for SCL to be released, before starting their high periods. A synchronized signal on SCL
is obtained, where the slowest device determines the length of the low period and the fastest device
determines the length of the high period.
If a device pulls down the clock line for a longer time, the result is that all clock generators must enter the
wait state. In this way, a slave slows down a fast master and the slow device creates enough time to store
a received byte or to prepare a byte to be transmitted.
Figure 14-11. Synchronization of Two I2C Clock Generators During Arbitration
14.2.8 Arbitration
If two or more master-transmitters attempt to start a transmission on the same bus at approximately the
same time, an arbitration procedure is invoked. The arbitration procedure uses the data presented on the
serial data bus (SDA) by the competing transmitters.
between two devices. The first master-transmitter, which release the SDA line high, is overruled by
another master-transmitter that drives SDA low. The arbitration procedure gives priority to the device that
transmits the serial data stream with the lowest binary value. Should two or more devices send identical
first bytes, arbitration continues on the subsequent bytes.
If the I2C module is the losing master, it switches to the slave-receiver mode, sets the arbitration lost (AL)
flag, and generates the arbitration-lost interrupt request.
If during a serial transfer the arbitration procedure is still in progress when a repeated START condition or
a STOP condition is transmitted to SDA, the master-transmitters involved must send the repeated START
condition or the STOP condition at the same position in the format frame. Arbitration is not allowed
between:
•
A repeated START condition and a data bit
•
A STOP condition and a data bit
•
A repeated START condition and a STOP condition
1016
C28 Inter-Integrated Circuit Module
Figure 14-11
illustrates the clock synchronization. The wired-AND property of
SCL from
device #1
SCL from
device #2
Bus line
SCL
Copyright © 2012–2019, Texas Instruments Incorporated
Wait
Start HIGH
state
period
Figure 14-12
illustrates the arbitration procedure
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
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