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Overview
24.1 Overview
The ARM
Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system
®
requirements of minimal memory implementation, reduced pin count, and low power consumption, while
delivering outstanding computational performance and exceptional system response to interrupts.
Features include:
•
32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
•
Outstanding processing performance combined with fast interrupt handling
•
Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core
in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few
kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
•
Fast code execution permits slower processor clock or increases sleep mode time
•
Harvard architecture characterized by separate buses for instruction and data
•
Efficient processor core, system and memories
•
Hardware division and fast multiplier
•
Deterministic, high-performance interrupt handling for time-critical applications
•
Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality
•
Enhanced system debug with extensive breakpoint and trace capabilities
•
Migration from the ARM7 processor family for better performance and power efficiency
•
Optimized for single-cycle Flash memory usage
•
Ultra-low power consumption with integrated sleep modes
This family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-
sensitive embedded microcontroller applications, such as factory automation and control, industrial control
power devices, building and home automation, and stepper motor control.
24.2 Block Diagram
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded applications. It delivers exceptional power efficiency
through an efficient instruction set and extensively optimized design, providing high-end processing
hardware including single-cycle 32x32 multiplication and dedicated hardware division.
To facilitate the design of cost-sensitive devices, this processor implements tightly coupled system
components that reduce processor area while significantly improving interrupt handling and system debug
capabilities. It implements a version of the Thumb
reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional
performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
This processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt
performance. The Concerto™ NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt
priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the
ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt
handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining
optimization also significantly reduces the overhead when switching from one ISR to another. To optimize
low-power designs, the NVIC integrates with the sleep modes, including deep-sleep mode, which enables
the entire device to be rapidly powered down. The block diagram is illustrated below.
1568
Cortex-M3 Processor
instruction set, ensuring high code density and
®
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUH22I – April 2012 – Revised November 2019
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