Register Map; Inter-Integrated Circuit (I2C) Interface Register Map - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Map

22.5 Register Map
Table 22-2 lists the I2C registers. All addresses given are relative to the I2C base address:
• I2C 0: 0x4002.0000
• I2C 1: 0x4002.1000
Note that the I2C module clock must be enabled before the registers can be programmed (see the System
Control chapter). There must be a delay of three system clocks after the I2C module clock is enabled
before any I2C module registers are accessed.
The hw_i2c.h file in the Concerto™ MWare library uses a base address of 0x800 for the I2C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that Concerto uses an
offset between 0x000 and 0x018 with the slave base address.
Offset
I2C Master
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
I2C Slave
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
1498
M3 Inter-Integrated Circuit (I2C) Interface
Table 22-2. Inter-Integrated Circuit (I2C) Interface Register Map
Name
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIMR
I2CSRIS
I2CSMIS
I2CSICR
Copyright © 2012–2019, Texas Instruments Incorporated
Type Reset
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0001
R/W 0x0000.0000
RO 0x0000.0000
RO 0x0000.0000
WO 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
RO 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
RO 0x0000.0000
RO 0x0000.0000
WO 0x0000.0000
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Description
I2C Master Slave Address
I2C Master Control/Status
I2C Master Data
I2C Master Timer Period
I2C Master Interrupt Mask
I2C Master Raw Interrupt
Status
I2C Master Masked Interrupt
Status
I2C Master Interrupt Clear
I2C Master Configuration
I2C Slave Own Address
I2C Slave Control/Status
I2C Slave Data
I2C Slave Interrupt Mask
I2C Slave Raw Interrupt Status
I2C Slave Masked Interrupt
Status
I2C Slave Interrupt Clear
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