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Figure 17-15. Single-Cycle Write Access, FRM50 = 0, FRMCNT = 0, WR2CYC = 0
Figure 17-16. Two-Cycle Read, Write Accesses, FRM50 = 0, FRMCNT = 0, RD2CYC = 1, WR2CYC = 1
CLOCK
(
)
EPI0S31
FRAME
(EPI0S30)
RD
(
)
EPI0S29
WR
(
)
EPI0S28
Address
Data
Figure 17-17. Read Accesses, FRM50 = 0, FRMCNT = 0, RD2CYC = 1
CLOCK
(
)
EPI0S31
FRAME
(EPI0S30)
RD
(
)
EPI0S29
WR
(
)
EPI0S28
Address
Data
SPRUH22I – April 2012 – Revised November 2019
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Clock
(
)
EPI0S31
Frame
(EPI0S30)
RD
(
)
EPI0S29
WR
(
)
EPI0S28
Address
Data
Data
Read
Addr1
Addr2
Data1
Copyright © 2012–2019, Texas Instruments Incorporated
Data
Data
Write
Addr3
Data2
Data3
External Peripheral Interface (EPI)
General-Purpose Mode
1219