Functional Description; Μdma Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description

Nested
Vectored
IRQ
Interrupt
Controller
(NVIC)
ARM
Cortex-M3
16.3 Functional Description
The µDMA controller is a flexible and highly configurable DMA controller designed to work efficiently with
the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address increment
schemes, multiple levels of priority among DMA channels, and several transfer modes to allow for
sophisticated programmed data transfers. The µDMA controller's usage of the bus is always subordinate
to the processor core, so it never holds up a bus transaction by the processor. Because the µDMA
controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free,
with no impact on the rest of the system. The bus architecture has been optimized to greatly enhance the
ability of the processor core and the µDMA controller to efficiently share the on-chip bus, thus improving
performance. The optimizations include RAM striping and peripheral bus segmentation, which in many
cases allow both the processor core and the µDMA controller to access the bus and perform simultaneous
data transfers.
The µDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash
memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash
memory or ROM with the µDMA controller.
Each peripheral function that is supported has a dedicated channel on the µDMA controller that can be
configured independently. The µDMA controller implements a unique configuration method using channel
control structures that are maintained in system memory by the processor. While simple transfer modes
are supported, it is also possible to build up sophisticated "task" lists in memory that allow the µDMA
controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer
request. The µDMA controller also supports the use of ping-pong buffering to accommodate constant
streaming of data to or from a peripheral.
Each channel also has a configurable arbitration size. The arbitration size is the number of items that are
transferred in a burst before the µDMA controller rearbitrates for channel priority. Using the arbitration
size, it is possible to control exactly how many items are transferred to or from a peripheral each time it
makes a µDMA service request.
1150
M3 Micro Direct Memory Access ( µDMA)
Figure 16-1. µDMA Block Diagram
DMA error
request
Peripheral
DMA Channel0 done
•
•
•
request
Peripheral
done
DMA ChannelN-1
General
request
Peripheral N
done
Registers
Copyright © 2012–2019, Texas Instruments Incorporated
uDMA
Controller
DMASTAT
DMACFG
DMACTLBASE
DMAALTBASE
DMAWAITSTAT
DMASWREQ
DMAUSEBURSTSET
DMAUSEBURSTCLR
DMAREQMASKSET
DMAREQMASKCLR
DMAENASET
DMAENACLR
DMAALTSET
DMAALTCLR
DMAPRIOSET
DMAPRIOCLR
DMAERRCLR
DMACHALT
DMACHAMP0
DMACHAMP1
DMACHAMP2
DMACHAMP3
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
System Memory
CH Control Table
DMASRCENDP
DMADSTENDP
DMACHCTRL
•
•
•
DMASRCENDP
DMADSTENDP
DMACHCTRL
Transfer Buffers
Used by DMA
µ
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