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21.7.12 UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
31
23
15
14
LME5MIS
LME1MIS
R-0
R-0
7
6
FEMIS
RTMIS
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-14. UART Masked Interrupt Status (UARTMIS) Register Field Descriptions
Bit
Field
31-16
Reserved
15
LME5MIS
14
LME1MIS
13
LMSBMIS
12-11
Reserved
10
OEMIS
9
BEMIS
8
PEMIS
7
FEMIS
SPRUH22I – April 2012 – Revised November 2019
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Figure 21-19. UART Masked Interrupt Status (UARTMIS) Register
13
12
LMSBMIS
R-0
5
4
TXMIS
RXMIS
R-0
R-0
Value
Description
Reserved
LIN Mode Edge 5 Masked Interrupt Status
This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR register.
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the 5th falling edge of the LIN Sync Field.
LIN Mode Edge 1 Masked Interrupt Status
This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR register.
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the 1st falling edge of the LIN Sync Field.
LIN Mode Sync Break Masked Interrupt Status
This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR register.
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receipt of a LIN Sync Break.
Reserved
UART Overrun Error Masked Interrupt Status
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to an overrun error.
UART Break Error Masked Interrupt Status
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a break error.
UART Parity Error Masked Interrupt Status
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a parity error.
UART Framing Error Masked Interrupt Status
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a framing error.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
Reserved
R-0
11
10
Reserved
OEMIS
R-0
R-0
3
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Register Descriptions
24
16
9
8
BEMIS
PEMIS
R-0
R-0
0
Reserved
R-0
1475
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