Error Status Clear Register (Err_Status_Clr); Error Counter Register (Err_Cnt); Error Status Clear Register (Err_Status_Clr) Field Descriptions; Error Counter Register (Err_Cnt) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Flash Registers

Error Status Clear Register (ERR_STATUS_CLR)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-101. Error Status Clear Register (ERR_STATUS_CLR) Field Descriptions

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-102. Error Counter Register (ERR_CNT) Field Descriptions

Internal Memory

Figure 5-97. Error Status Clear Register (ERR_STATUS_CLR)

Uncorrectable error clear. Writing a 1 to this bit will clear the UNC_ERR bit of ERR_STATUS

Fail on 1 clear. Writing a 1 to this bit will clear the FAIL_1 bit of ERR_STATUS register. Writes of 0

have no effect.

Fail on 0 clear. Writing a 1 to this bit will clear the FAIL_0 bit of ERR_STATUS register. Writes of 0

have no effect.

Figure 5-98. Error Counter Register (ERR_CNT)

Single bit error count. This counter increments with every single bit ECC error occurrence. Upon

reaching the threshold value counter stops counting on single bit errors. ERR_CNT can be cleared

(irrespective of whether threshold is met or not) using "Single Err Int Clear" bit. This is applicable for

ECC logic test mode and normal operational mode. In ECC logic test mode, ERR_CNT will keep

incrementing for every cycle after a single bit error occurrence. So, in order to clear ERR_CNT in

ECC logic test mode, ECC logic test mode has to be disabled prior to clearing the ERR_CNT using

"Single Err Int Clear" bit.

SPRUH22I – April 2012 – Revised November 2019

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