Ecc Test Address Register (Faddr_Test); Ecc Test Register (Fecc_Test); Ecc Control Register (Fecc_Ctrl); Ecc Test Address Register (Faddr_Test) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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5.4.2.13 ECC Test Address Register (FADDR_TEST)

31
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-108. ECC Test Address Register (FADDR_TEST) Field Descriptions
Bit Field
31-19 Reserved
18-0 ADDR

5.4.2.14 ECC Test Register (FECC_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-8 Reserved
7-0 ECC

5.4.2.15 ECC Control Register (FECC_CTRL)

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-110. ECC Control Register (FECC_CTRL) Field Descriptions
Bit Field
31-2 Reserved
1 ECC_SELECT
0 ECC_TEST_EN
SPRUH22I – April 2012 – Revised November 2019
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Figure 5-104. ECC Test Address Register (FADDR_TEST)
19 18
Value Description
Reserved
Address for selected 64-bit data. User-configurable address bits of the selected data in
ECC test mode.
Figure 5-105. ECC Test Register (FECC_TEST)
Reserved
R-0
Table 5-109. ECC Test Register (FECC_TEST) Field Descriptions
Value Description
Reserved
8-bit ECC for selected 64-bit data. User-configurable ECC bits of the selected 64-bit
data block in ECC test mode.
Figure 5-106. ECC Control Register (FECC_CTRL)
Reserved
R-0
Value Description
Reserved
ECC block select.
0 Selects the ECC block on bits [63:0] of bank data.
1 Selects the ECC block on bits [127:64] of bank data.
ECC test mode enable.
0 ECC test mode disabled
1 ECC test mode enabled
Copyright © 2012–2019, Texas Instruments Incorporated
ADDR
R/W-0
Reserved
R-0
2
ECC_SELECT
Flash Registers
8 7
ECC
R/W-0
1 0
ECC_TEST_EN
R/W-0 R/W-0
Internal Memory
0
0
16
523