Dma Peripheral Identification 4 (Dmaperiphid4), Offset 0Xfd0; Dma Primecell Identification 0 (Dmapcellid0), Offset 0Xff0; Dma Primecell Identification 1 (Dmapcellid1), Offset 0Xff4; Dma Peripheral Identification 4 (Dmaperiphid4) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

µDMA Register Descriptions

Table 16-41. DMA Peripheral Identification 3 (DMAPeriphID3) Register Field Descriptions

16.7.27 DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0

The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset

Figure 16-36. DMA Peripheral Identification 4 (DMAPeriphID4) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-42. DMA Peripheral Identification 4 (DMAPeriphID4) Register Field Descriptions

The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values.

Figure 16-37. DMA PrimeCell Identification 0 (DMAPCellID0) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-43. DMA PrimeCell Identification 0 (DMAPCellID0) Register Field Descriptions

The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values.

Figure 16-38. DMA PrimeCell Identification 1 (DMAPCellID1) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

M3 Micro Direct Memory Access ( µDMA)

µDMA Peripheral ID Register [31:24]

Can be used by software to identify the presence of this peripheral.

µDMA Peripheral ID Register

Can be used by software to identify the presence of this peripheral.

µDMA PrimeCell ID Register [7:0]

Provides software a standard cross-peripheral identification system.

SPRUH22I – April 2012 – Revised November 2019

Submit Documentation Feedback

Table of Contents