Spi Serial Transmit Buffer Register (Spitxbuf) - Address 7048H; Spi Serial Data Register (Spidat) - Address 7049H; Spi Serial Transmit Buffer Register (Spitxbuf) Field Descriptions; Spi Serial Data Register (Spidat) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 12-19. SPI Serial Transmit Buffer Register (SPITXBUF) — Address 7048h
15 14
TXB15 TXB14
R-0 R-0
7 6
TXB7 TXB6
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-15. SPI Serial Transmit Buffer Register (SPITXBUF) Field Descriptions
Bit Field
15-0 TXB15 − TXB0
12.3.1.8 SPI Serial Data Register (SPIDAT)
SPIDAT is the transmit/receive shift register. Data written to SPIDAT is shifted out (MSB) on subsequent
SPICLK cycles. For every bit (MSB) shifted out of the SPI, a bit is shifted into the LSB end of the shift
register.
Figure 12-20. SPI Serial Data Register (SPIDAT) — Address 7049h
15 14
SDAT15 SDAT14
R-0 R-0
7 6
SDAT7 SDAT6
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15-0 SDAT15 −
SDAT0
SPRUH22I – April 2012 – Revised November 2019
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13 12
TXB13 TXB12
R-0 R-0
5 4
TXB5 TXB4
R-0 R-0
Value Description
Transmit Data Buffer. This is where the next character to be transmitted is stored. When the
transmission of the current character has completed, if the TX BUF FULL Flag bit is set, the
contents of this register is automatically transferred to SPIDAT, and the TX BUF FULL Flag is
cleared.
Writes to SPITXBUF must be left-justified.
13 12
SDAT13 SDAT12
R-0 R-0
5 4
SDAT5 SDAT4
R-0 R-0
Table 12-16. SPI Serial Data Register (SPIDAT) Field Descriptions
Value Description
Serial data. Writing to the SPIDAT performs two functions:
• It provides data to be output on the serial output pin if the TALK bit (SPICTL.1) is set.
• When the SPI is operating as a master, a data transfer is initiated. When initiating a transfer, see
the CLOCK POLARITY bit (SPICCR.6) described in
(SPICTL.3) described in
In master mode, writing dummy data to SPIDAT initiates a receiver sequence. Since the data is not
hardware-justified for characters shorter than sixteen bits, transmit data must be written in left-
justified form, and received data read in right-justified form.
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
TXB11 TXB10
R-0 R-0
3 2
TXB3 TXB2
R-0 R-0
11 10
SDAT11 SDAT10
R-0 R-0
3 2
SDAT3 SDAT2
R-0 R-0
Section 12.3.1.1
Section 12.3.1.2, for the requirements.
C28 Serial Peripheral Interface (SPI)
SPI Registers and Waveforms
9 8
TXB9 TXB8
R-0 R-0
1 0
TXB1 TXB0
R-0 R-0
9 8
SDAT9 SDAT8
R-0 R-0
1 0
SDAT1 SDAT0
R-0 R-0
and the CLOCK PHASE bit
969