SPI Registers and Waveforms
Figure 12-28. CLOCK POLARITY = 1, CLOCK PHASE = 1 (All data transitions are during the falling edge,
976
C28 Serial Peripheral Interface (SPI)
but delayed by half clock cycle. Inactive level is high.)
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Ch1 Period
200 ns
SPICLK
SPISIMO
SPRUH22I – April 2012 – Revised November 2019
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