Flash Prefetch Mode - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

1. If the destination address is within the flash or OTP, the prefetch aborts and then resumes at the

destination address.

2. If the destination address is outside of the flash and OTP, the prefetch is aborted and begins again

only when a branch is made back into the flash or OTP. The flash prefetch mechanism only applies to

instruction fetches from program space. ata reads from data memory and from program memory do

not utilize the prefetch buffer capability and thus bypass the prefetch buffer. For example, instructions

such as MAC, DMAC, and PREAD read a data value from program memory. When this read happens,

the prefetch buffer is bypassed but the buffer is not flushed. If an instruction prefetch is already in

progress when a data read operation is initiated, then the data read will be stalled until the prefetch

Flash prefetch

5.3.8.2.2.1 Data Cache

Along with the prefetch mechanism, a data cache of 128 bits width is also implemented to improve data

space read and program space read performance. This data cache will not be filled by the prefetch

mechanism. When any kind of data-space read or program-space read is made by the CPU from an

address in the bank, and if the data corresponding to the requested address is not in the data cache, then

128 bits of data will be read from the bank and is loaded in the data cache. This data is eventually sent to

the CPU for processing. The starting address of the access from flash is automatically aligned to a 128-bit

boundary such that the requested address location is within the 128 bits to be read from the bank. By

default, this data cache is disabled and can be enabled by setting DATA_CACHE_EN bit in the

FRD_INTF_CTRL register.

Some other points to keep in mind when working with C28x flash:

Reads of the CSM password locations, ECSLKEY and EXEONLY locations are hardwired for 10 wait-

states. The RWAIT bits have no effect on these locations

CPU writes to the flash or OTP memory map areas are ignored. They complete in a single cycle.

If C28x security zone is in the locked state and the respective password lock bits are not all 1s, then,

– Data reads to C28X-Z1-CSMPSWD, C28x-Z1-ECSLPSWD will return 0.

SPRUH22I – April 2012 – Revised November 2019

Submit Documentation Feedback

Figure 5-80. Flash Prefetch Mode

Instruction buffer

Instruction fetch

Data read either from program or data memory

Flash or OTP Read (128-bit)

Flash Controller Memory Module

Flash and OTP

Internal Memory

Chapters

Table of Contents