Dma Operation; Remainder (Maxload/4); Actual Bytes Read; Packet Sizes That Clear Rxrdy - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description
When the USB OTG controller B device has finished using the bus, the USB controller goes into
SUSPEND mode by setting the SUSPEND bit in the USBPOWER register. The A device detects this and
either terminates the session or reverts to Host mode. If the A device is USB OTG controller, it generates
a disconnect interrupt.

18.2.4 DMA Operation

The USB peripheral provides an interface connected to the μDMA controller with separate channels for
three transmit endpoints and 3 receive endpoints. Software selects which endpoints to service with the
μDMA channels using the USB DMA Select (USBDMASEL) register. The μDMA operation of the USB is
enabled through the USBTXCSRHn and USBRXCSRHn registers, for the TX and RX channels
respectively. When μDMA operation is enabled, the USB asserts a μDMA request on the enabled receive
or transmit channel when the associated FIFO can transfer data. When either FIFO can transfer data, the
burst request for that channel is asserted. The μDMA channel must be configured to operate in Basic
mode, and the size of the μDMA transfer must be restricted to whole multiples of the size of the USB
FIFO. Both read and write transfers of the USB FIFOs using μDMA must be configured in this manner. For
example, if the USB endpoint is configured with a FIFO size of 64 bytes, the μDMA channel can be used
to transfer 64 bytes to or from the endpoint FIFO. If the number of bytes to transfer is less than 64, then a
programmed I/O method must be used to copy the data to or from the FIFO.
If the DMAMOD bit in the USBTXCSRHn/USBRXCSRHn register is clear, an interrupt is generated after
every packet is transferred, but the μDMA continues transferring data. If the DMAMOD bit is set, an
interrupt is generated only when the entire μDMA transfer is complete. The interrupt occurs on the USB
interrupt vector. Therefore, if interrupts are used for USB operation and the μDMA is enabled, the USB
interrupt handler must be designed to handle the μDMA completion interrupt.
Care must be taken when using the μDMA to unload the receive FIFO as data is read from the receive
FIFO in 4 byte chunks regardless of value of the MAXLOAD field in the USBRXCSRHn register. The
RXRDY bit is cleared as follows.
Value
0
1
2
3
Value
0
1
2
3
Value
0
1
2
3
1290
M3 Universal Serial Bus (USB) Controller
Table 18-1. Remainder (MAXLOAD/4)
Description
MAXLOAD = 64 bytes
MAXLOAD = 61 bytes
MAXLOAD = 62 bytes
MAXLOAD = 63 bytes
Table 18-2. Actual Bytes Read
Description
MAXLOAD
MAXLOAD +3
MAXLOAD +2
MAXLOAD +1
Table 18-3. Packet Sizes That Clear RXRDY
Description
MAXLOAD, MAXLOAD-1, MAXLOAD-2, MAXLOAD-3
MAXLOAD
MAXLOAD, MAXLOAD-1
MAXLOAD, MAXLOAD-1, MAXLOAD-2
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SPRUH22I – April 2012 – Revised November 2019
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