Table of Contents
Advertisement
SSI Registers
20.5.2.2 SSICR1 Register (Offset = 4h) [reset = 0h]
SSICR1 is shown in
Return to the
Summary
SSI Control 1
31
30
23
22
15
14
RESERVED
R-0h
7
6
Bit
Field
31-13
RESERVED
10
FSSHLDFRM
9
HSCLKEN
8
DIR
4
EOT
1424
M3 Synchronous Serial Interface (SSI)
Figure 20-11
and described in
Table.
Figure 20-11. SSICR1 Register
29
28
RESERVED
21
20
RESERVED
13
12
5
4
EOT
R/W-0h
Table 20-5. SSICR1 Register Field Descriptions
Type
Reset
R
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
Copyright © 2012–2019, Texas Instruments Incorporated
Table
20-5.
27
26
R-0h
19
18
R-0h
11
10
FSSHLDFRM
R/W-0h
3
2
MS
R/W-0h
Description
Reserved
FSS Hold Frame
Value Description
0 Pulse SSInFss at every byte (the bit DSS in the SSICR0 register
must be set to 0x7 (data size 8 bits) in thisconfiguration)
1 Hold SSInFss for the whole frame
Reset type: PER.RESET
High Speed Clock
Enable High speed clock enable is available only when operating as
a master.
Value Description
0 Use Input Clock
1 Use High Speed Clock
Note: For proper functionality of high speed mode, the HSCLKEN bit
in the SSICR1 register should be set before any SSI data
transfer or after applying a reset to the QSSI module. In addition, the
SSE bit must be set to 0x1 before the HSCLKEN bit is set.
Reset type: PER.RESET
SSI Direction of Operation
Value Description
0 TX (Transmit Mode) write direction
1 RX (Receive Mode) read direction
Reset type: PER.RESET
End of Transmission
This bit is only valid for Master mode devices and operations (
=0x0).MS
Value Description
0 The TXRIS interrupt indicates that the transmit FIFO is half full or
less.
1 The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.When using uDMA, the DMATX bit cannot be set to 1 in any
mode. If used with uDMA, it prevents RISEOT from asserting. If the
bit is kept at 0 during operation, an interrupt is still generated when
the TX FIFO is half or less full with or without using the uDMA.EOT
(Legacy)
Reset type: PER.RESET
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
25
24
17
16
9
8
HSCLKEN
DIR
R/W-0h
R/W-0h
1
0
SSE
LBM
R/W-0h
R/W-0h
Submit Documentation Feedback
Advertisement
Chapters
Table of Contents
