Set The Receive Clock Polarity; Receive Clock Signal Source Selection; Register Bit Used To Set Receive Clock Polarity - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com
Table 15-40. Register Bits Used to Set the Receive Clock Mode (continued)
Register Bit
SPCR1 12-11
15.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
Table 15-41 shows how you can select various sources to provide the receive clock signal and affect the
MCLKR pin. The polarity of the signal on the MCLKR pin is determined by the CLKRP bit.
In the digital loopback mode (DLB = 1), the transmit clock signal is used as the receive clock signal.
Also, in the clock stop mode, the internal receive clock signal (MCLKR) and the internal receive frame-
synchronization signal (FSR) are internally connected to their transmit counterparts, CLKX and FSX.
DLB in CLKRM in
SPCR1 PCR
0 0
0 1
1 0
1 1

15.8.18 Set the Receive Clock Polarity

Register Bit
PCR 0
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Name Function
CLKSTP Clock stop mode
CLKSTP = 0Xb
CLKSTP = 10b
CLKSTP = 11b
Table 15-41. Receive Clock Signal Source Selection
Source of Receive Clock
The MCLKR pin is an input driven by an
external clock. The external clock signal is
inverted as determined by CLKRP before
being used.
The sample rate generator clock (CLKG)
drives internal MCLKR.
Internal CLKX drives internal MCLKR. To
configure CLKX, see Section
Transmit Clock Mode.
Internal CLKX drives internal MCLKR. To
configure CLKX, see Section
Transmit Clock Mode.
Table 15-42. Register Bit Used to Set Receive Clock Polarity
Name Function
CLKRP Receive clock polarity
CLKRP = 0
CLKRP = 1
Copyright © 2012–2019, Texas Instruments Incorporated
Clock stop mode disabled; normal clocking for
non-SPI mode.
Clock stop mode enabled without clock delay.
The internal receive clock signal (MCLKR) and
the internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.
Clock stop mode enabled with clock delay. The
internal receive clock signal (MCLKR) and the
internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.
MCLKR Pin Status
Input
Output. CLKG, inverted as determined by CLKRP,
is driven out on the MCLKR pin.
High impedance
15.9.18, Set the
Output. Internal MCLKR (same as internal CLKX)
15.9.18, Set the is inverted as determined by CLKRP before being
driven out on the MCLKR pin.
Receive data sampled on falling edge of MCLKR
Receive data sampled on rising edge of MCLKR
C28 Multichannel Buffered Serial Port (McBSP)
Receiver Configuration
Reset
Type Value
R/W 00
Reset
Type Value
R/W 0
1093