System Timer (Systick) Register Descriptions; Systick Control And Status Register (Stctrl), Offset 0X010; Systick Control And Status Register (Stctrl); Systick Control And Status Register (Stctrl) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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25.4 System Timer (SysTick) Register Descriptions

This section lists and describes the System Timer registers, in numerical order by address offset.

25.4.1 SysTick Control and Status Register (STCTRL), offset 0x010

The SysTick Control and Status Register (STCTRL) register enables the SysTick features.
Note: This register can only be accessed from privileged mode.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-8. SysTick Control and Status Register (STCTRL) Field Descriptions
Bit Field
31-17 Reserved
16 COUNT
15-3 Reserved
2 CLK_SRC
1 INTEN
0 ENABLE
SPRUH22I – April 2012 – Revised November 2019
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Figure 25-2. SysTick Control and Status Register (STCTRL)
Reserved
Reserved
R-0
Value Description
Reserved
Count Flag
0 The SysTick timer has not counted to 0 since the last time this bit was read. 0
1 The SysTick timer has counted to 0 since the last time this bit was read.
This bit is cleared by a read of the register or if the STCURRENT register is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP
Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the
ARM® Debug Interface V5 Architecture Specification for more information on MasterType.
Reserved
Clock Source
0 External reference clock. (Not implemented for Concerto microcontrollers.)
1 System clock
Because an external reference clock is not implemented, this bit must be set in order for SysTick to
operate.
Interrupt Enable
0 Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has
ever reached 0.
1 An interrupt is generated to the NVIC when SysTick counts to 0.
Enable
0 The counter is disabled.
1 Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and
begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled
by INTEN. The counter then loads the RELOAD value again and begins counting.
Copyright © 2012–2019, Texas Instruments Incorporated
System Timer (SysTick) Register Descriptions
R-0
3
CLK_SRC
R/W-1
17
2 1
INTEN
R/W-0
Cortex-M3 Peripherals
16
COUN
T
R-0
0
ENABLE
R/W-0
1609