Ssimis Register; Ssimis Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

SSI Registers
20.5.2.8 SSIMIS Register (Offset = 1Ch) [reset = 0h]
SSIMIS is shown in
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SSI Masked Interrupt Status
31 30
23 22
15 14
7 6
RESERVED EOTMIS
R-0h R-0h
Bit Field
31-7 RESERVED
6 EOTMIS
5 DMATXMIS
4 DMARXMIS
3 TXMIS
1432
M3 Synchronous Serial Interface (SSI)
Figure 20-17 and described in
Table.
Figure 20-17. SSIMIS Register
29 28
RESERVED
21 20
RESERVED
13 12
RESERVED
5 4
DMATXMIS DMARXMIS
R-0h R-0h
Table 20-11. SSIMIS Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2012–2019, Texas Instruments Incorporated
Table 20-11.
27 26
R-0h
19 18
R-0h
11 10
R-0h
3 2
TXMIS RXMIS
R-0h R-0h
Description
Reserved
End of Transmit Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to the transmission of the
last data bit.This bit is cleared when a 1 is written to the EOTIC bit in
the SSI Interrupt Clear (SSIICR) register.
Reset type: PER.RESET
SSI Transmit DMA Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due tothe completion of the
transmit DMA.This bit is cleared when a 1 is written to the DMATXIC
bit in the SSI Interrupt Clear (SSIICR) register.
Reset type: PER.RESET
SSI Receive DMA Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to the completion of the
receive DMA.This bit is cleared when a 1 is written to the DMARXIC
bit in the SSI Interrupt Clear (SSIICR) register.
Reset type: PER.RESET
SSI Transmit FIFO Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to the transmit FIFO
being half empty or less. (if the EOT bit is clear) or due to the
transmission of the last data bit (if the EOT bit is set)This bit is
cleared when the transmit FIFO is more than half empty .(if the EOT
bit is clear) or when it has any data in it (if the EOT bit is set)
Reset type: PER.RESET
SPRUH22I – April 2012 – Revised November 2019
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25 24
17 16
9 8
1 0
RTMIS RORMIS
R-0h R-0h
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