Usb Transmit Control And Status Endpoint N Low Register (Usbtxcsrl[N]) In Otg B/Device Mode; Usb Transmit Control And Status Endpoint N Low Register (Usbtxcsrl[N]) In Otg B/Device Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions
Table 18-44. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
Bit Field Value
0 TXRDY
0
1
The USBTXCSRL[n] registers in OTG B/Device Mode are shown in
Figure 18-42.
Figure 18-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
7 6
Reserved CLRDT
R-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-45. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
Bit Field Value
7 Reserved 0
6 CLRDT
0
1
5 STALLED
0
1
4 STALL
0
1
3 FLUSH
0
1
2 UNDRN
0
1
1 FIFONE
0
1
1340
M3 Universal Serial Bus (USB) Controller
in OTG A/Host Mode Field Descriptions (continued)
Description
Transmit Packet Ready.
This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS
register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
No transmit packet is ready.
Software sets this bit after loading a data packet into the TX FIFO.
in OTG B/Device Mode
5 4
STALLED STALL
R/W-0 R/W-0
in OTG B/Device Mode Field Descriptions
Description
Reserved
Clear Data Toggle
No effect
Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register.
Endpoint Stalled. Software must clear this bit.
A STALL handshake has not been transmitted.
A STALL handshake has been transmitted. The FIFO is flushed and the TXRDY bit is cleared.
Send Stall. Software clears this bit to terminate the STALL condition.
Note: This bit has no effect in isochronous transfers.
No effect
Issues a STALL handshake to an IN token.
Flush FIFO. This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently
being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice
to completely clear the FIFO.
Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be
corrupted.
No effect
Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit
is cleared. The EPn bit in the USBTXIS register is also set in this situation.
This bit is cleared automatically.
Underrun. Software must clear this bit.
No underrun
An IN token has been received when TXRDY is not set.
FIFO Not Empty
The FIFO is empty.
At least one packet is in the transmit FIFO.
Copyright © 2012–2019, Texas Instruments Incorporated
Table 18-44
3 2
FLUSH UNDRN
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
and described in
1 0
FIFONE TXRDY
R/W-0 R/W-0
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