General-Purpose Mode; Two-Entry Fifo - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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FFULL
( )
EPI0S27
FEMPTY
( )
EPI0S26
CS
( )
EPI0S30
WR
( )
EPI0S29
RD
( )
EPI0S28
Data

17.8 General-Purpose Mode

The General-Purpose Mode Configuration (EPIGPCFG) register is used to configure the control, data, and
address pins, if used. Any unused EPI controller signals can be used as GPIOs or another alternate
function. The general-purpose configuration can be used for custom interfaces with FPGAs, CPLDs, and
digital data acquisition and actuator control.
NOTE: The RD2CYC bit in the EPIGPCFG register must be set at all times in General-Purpose
mode to ensure proper operation.
General-Purpose mode is designed for three general types of use:
• Extremely high-speed clocked interfaces to FPGAs and CPLDs. Three sizes of data and optional
address are supported. Framing and clock-enable functions permit more optimized interfaces.
• General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely controlled
by the EPIBAUD register baud rate (when used with the WFIFO and/or the NBRFIFO) or by the rate of
accesses from software or µDMA. Examples of this type of use include:
– Reading 20 sensors at fixed time periods by configuring 20 pins to be inputs, configuring the
COUNT0 field in the EPIBAUD register to some divider, and then using non-blocking reads.
– Implementing a very wide ganged PWM/PCM with fixed frequency for driving actuators, LEDs, etc.
– Implementing SDIO 4-bit mode where commands are driven or captured on six pins with fixed
timing, fed by the µDMA.
• General custom interfaces of any speed.
The configuration allows for choice of an output clock (free-running or gated), a framing signal (with frame
size), a ready input (to stretch transactions), an address (of varying sizes), and data (of varying sizes).
Additionally, provisions are made for separating data and address phases.
The interface has the following optional features:
• Use of the EPI clock output is controlled by the CLKPIN bit in the EPIGPCFG register. Unclocked uses
include general-purpose I/O and asynchronous interfaces (optionally using RD and WR strobes).
Clocked interfaces allow for higher speeds and are much easier to connect to FPGAs and CPLDs
(which usually include input clocks).
• EPI clock, if used, may be free running or gated depending on the CLKGATE bit in the EPIGPCFG
register. A free-running EPI clock requires another method for determining when data is live, such as
the frame pin or RD/WR strobes. A gated clock approach uses a setup-time model in which the EPI
clock controls when transactions are starting and stopping. The gated clock is held high until a new
transaction is started and goes high at the end of the cycle where RD/WR/FRAME and address (and
data if write) are emitted.
SPRUH22I – April 2012 – Revised November 2019
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Figure 17-14. Two-Entry FIFO
Data
Copyright © 2012–2019, Texas Instruments Incorporated
Data
External Peripheral Interface (EPI)
General-Purpose Mode
Data
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