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TEX
S
1BB
0
1BB
1
Table 25-4
shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4-
0x7.
Encoding, AA or BB
00
01
10
11
Table 25-5
shows the AP encodings in the MPUATTR register that define the access permissions for
privileged and unprivileged software.
AP Bit Field
000
001
010
011
100
101
110
111
25.2.4.2.1 MPU Configuration for a Concerto Microcontroller
Concerto microcontrollers' MPU should be programmed as shown in
Table 25-6. Memory Region Attributes for Concerto Microcontrollers
Memory Region
Flash memory
Internal SRAM
SPRUH22I – April 2012 – Revised November 2019
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Table 25-3. TEX, S, C, and B Bit Field Encoding (continued)
C
B
A
A
A
A
Table 25-4. Cache Policy for Memory Attribute Encoding
Table 25-5. AP Bit Field Encoding
Privileged Permissions
No access
R/W
R/W
R/W
Unpredictable
RO
RO
RO
TEX
S
000b
0
000b
1
Copyright © 2012–2019, Texas Instruments Incorporated
Memory Type
Shareability
Normal
Not shareable
Normal
Shareable
Corresponding Cache Policy
Non-cacheable
Write back, write and read allocate
Write through, no write allocate
Write back, no write allocate
Unprivileged Permissions
No access
No access
RO
R/W
Unpredictable
No access
RO
RO
Table
25-6.
C
B
1
0
1
0
Functional Description
Other Attributes
Cached memory
(BB = outer policy,
AA = inner policy).
See
Table 25-4
for
the encoding of the
AA and BB bits.
Description
All accesses generate a
permission fault.
Access from privileged
software only.
Writes by unprivileged software
generate a permission fault.
Full access.
Reserved.
Reads by privileged software
only.
Read-only, by privileged or
unprivileged software.
Read-only, by privileged or
unprivileged software.
Memory Type and
Attributes
Normal memory,
non-shareable,
write-through
Normal memory,
shareable, write-
through
1605
Cortex-M3 Peripherals
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