C28 Spi-A To M3 Ssi3 Internal Loopback; Spi Digital Audio Receiver Configuration Using 2 Spis; Standard Right-Justified Digital Audio Data Format - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 12-10. SPI Digital Audio Receiver Configuration Using 2 SPIs
Standard 28x SPI timing requirements limit the number of digital audio interface formats supported using
the 2-SPI configuration with the STEINV bit. See your device-specific data sheet electricals for SPI timing
requirements. With the SPI clock phase configured such that the CLOCK POLARITY (SPICCR.6) bit is 0
and the CLOCK PHASE (SPICTL.3) bit is 1 (data latched on rising edge of clock), standard right-justified
digital audio interface data format is supported as shown in
Figure 12-11. Standard Right-Justified Digital Audio Data Format
L/R CLK
AUDIO BIT CLK
DATA OUT

12.2 C28 SPI-A to M3 SSI3 Internal Loopback

The C28 SPI-A peripheral can be internally connected to the M3 SSI peripheral. External GPIO pins are
not used when the loopback feature is enabled and can be used for other functions.
Figure 12-12 illustrates the loopback connections between the M3 SSI3 and C28 SPI-A. The internal
connection logic block handles the signal routing between the peripherals and the GPIO mux.
SPRUH22I – April 2012 – Revised November 2019
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SPICLKA
SPISIMOA
SPI-A
SPISOMIA
SPISTEA
SPI-B Receive ( SPISTE invert)
L-channel
n n-1
0
Copyright © 2012–2019, Texas Instruments Incorporated
SPICLKB
SPISIMOB
SPISOMIB
SPISTEB
DIGITAL
AUDIO
RECEiVER
Figure 12-11.
1/fs
SPI-A Receive (normal
R-channel
n n-1
2 1 0
C28 SPI-A to M3 SSI3 Internal Loopback
SPI-B
SPISTE )
SPISTEA/B
SPICLKA/B
SPISIMOA/B
2 1 0
C28 Serial Peripheral Interface (SPI)
961