Mtoc_Msg_Ram Test And Initialization Register (Mtocrtestinit); Mtoc_Msg_Ram Test And Initialization Register (Mtocrtestinit) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

RAM Control Module Registers
5.2.1.9

MTOC_MSG_RAM Test and Initialization Register (MTOCRTESTINIT)

Figure 5-12. MTOC_MSG_RAM Test and Initialization Register (MTOCRTESTINIT)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-17. MTOC_MSG_RAM Test and Initialization Register (MTOCRTESTINIT) Field Descriptions
Bit Field
31-2 Reserved
1 ECCPARTEST
MTOCMSGRAM
0 RAMINIT
MTOCMSGRAM
448
Internal Memory
Reserved
R-0
Value Description
Reserved
Enable/Disable RAMTEST Feature for MTOC_MSG_RAM Block
0 RAMTEST feature is disabled for MTOC_MSG_RAM block.
1 RAMTEST feature is enabledd for MTOC_MSG_RAM block.
RAM Initialization for MTOC_MSG_RAM Block. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of MTOC_MSG_RAM block with data 0x0 and corresponding data
and address ECC/parity bits.
Copyright © 2012–2019, Texas Instruments Incorporated
2 1
ECCPARTEST
MTOCMSGRA
M
R/W-0
SPRUH22I – April 2012 – Revised November 2019
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0
RAMINIT
MTOCMSGRA
M
R/W-0