Dcbevt1 Event Triggering; Dcbevt2 Event Triggering - Texas Instruments Concerto F28M35 Series Technical Reference Manual

ePWM Submodules
The diagrams below show how the DCBEVT1, DCBEVT2 or DCEVTFLT signals are processed to
generate the digital compare B event force, interrupt, soc and sync signals.
DCBCTL[EVT1SRCSEL]
1
DCEVTFILT
async
DCBEVT1
0
TZFRC[DCBEVT1]
DCBCTL[EVT2SRCSEL]
DCEVTFILT 1
async
DCBEVT2
0
TZFRC[DCBEVT2]
7.2.9.4.2 Event Filtering
The DCAEVT1/2 and DCBEVT1/2 events can be filtered via event filtering logic to remove noise by
optionally blanking events for a certain period of time. This is useful for cases where the analog
comparator outputs may be selected to trigger DCAEVT1/2 and DCBEVT1/2 events, and the blanking
logic is used to filter out potential noise on the signal prior to tripping the PWM outputs or generating an
interrupt or ADC start-of-conversion. The event filtering can also capture the TBCTR value of the trip
event. The diagram below shows the details of the event filtering logic.
704
C28 Enhanced Pulse Width Modulator (ePWM) Module
Figure 7-51. DCBEVT1 Event Triggering
DCBCTL[EVT1FRCSYNCSEL]
1
Sync
0
TBCLK
Figure 7-52. DCBEVT2 Event Triggering
DCBCTL[EVT2FRCSYNCSEL]
1
Sync
0
TBCLK
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TZEINT[DCBEVT1]
set
Latch
clear
TZCLR[DCBEVT1] TZFLG[DCBEVT1]
DCBCTL[EVT1SOCE]
DCBCTL[EVT1SYNCE]
TZEINT[DCBEVT2]
set
Latch
clear
TZCLR[DCBEVT2] TZFLG[DCBEVT2]
SPRUH22I – April 2012 – Revised November 2019
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DCBEVT1.force
DCBEVT1.inter
DCBEVT1.soc
DCBEVT1.sync
DCBEVT2.force
DCBEVT2.inter