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System Control Block (SCB) Register Descriptions
25.6 System Control Block (SCB) Register Descriptions
The System Control Block (SCB) registers are shown in numerical order by address offset. They can only
be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and SYSPRI1-
SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses. The
processor does not support unaligned accesses to system control block registers.
25.6.1 Auxiliary Control (ACTLR) Register, offset 0x008
The Auxiliary Control (ACTLR) register provides disable bits for IT folding, write buffer use for accesses to
the default memory map, and interruption of multi-cycle instructions. By default, this register is set to
provide optimum performance from the Cortex-M3 processor and does not normally require modification.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-38. Auxiliary Control (ACTLR) Register Field Descriptions
Bit
Field
31-3
Reserved
2
DISFOLD
1
DISWBUF
0
DISMCYC
1628
Cortex-M3 Peripherals
Figure 25-32. Auxiliary Control (ACTLR) Register
Reserved
R-0
Value
Description
Reserved
Disable IT Folding
0
No effect
1
Disables IT folding
In some situations, the processor can start executing the first instruction in an IT block while it is still
executing the IT instruction. This behavior is called IT folding, and improves performance. However,
IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before
executing the task to disable IT folding.
Disable Write Buffer
0
No effect.
1
Disables write buffer use during default memory map accesses. In this situation, all bus faults are
precise bus faults but performance is decreased because any store to memory must complete
before the processor can execute the next instruction.
Note: This bit only affects write buffers implemented in the Cortex-M3 processor.
Disable Interrupts of Multiple Cycle Instructions
0
No effect.
1
Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt
latency of the processor is increased because any LDM or STM must complete before the
processor can stack the current state and enter the interrupt handler.
Copyright © 2012–2019, Texas Instruments Incorporated
3
2
1
DISFOLD
DISWBUF
R/W-0
R/W-0
SPRUH22I – April 2012 – Revised November 2019
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0
DISMCYC
R/W-0
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