Sx Shram Master Select Register (Msxmsel); Sx Shram Master Select Register (Msxmsel) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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5.2.1.3

Sx SHRAM Master Select Register (MSxMSEL)

31
15
7 6
S7MSEL S6MSEL
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. Sx SHRAM Master Select Register (MSxMSEL) Field Descriptions
Bit Field
31-8 Reserved
7 S7MSEL
6 S6MSEL
5 S5MSEL
4 S4MSEL
3 S3MSEL
2 S2MSEL
1 S1MSEL
SPRUH22I – April 2012 – Revised November 2019
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Figure 5-6. Sx SHRAM Master Select Register (MSxMSEL)
5 4
S5MSEL S4MSEL
R/W-0 R/W-0
Value Description
Reserved
Master Ownership for S7 RAM Block
0 M3 subsystem is master for S7 RAM block. M3 CPU/µDMA accesses are allowed based on the
setting of protection bits in the MSxSRCR register.
1 C28 subsystem is master for S7 RAM block. C28 CPU/DMA accesses are allowed based on the
setting of protection bits in the CSxSRCR register.
Master Ownership for S6 RAM Block
0 M3 subsystem is master for S6 RAM block. M3 CPU/µDMA accesses are allowed based on the
setting of protection bits in the MSxSRCR register.
1 C28 subsystem is master for S6 RAM block. C28 CPU/DMA accesses are allowed based on the
setting of protection bits in the CSxSRCR register.
Master Ownership for S5 RAM Block
0 M3 subsystem is master for S5 RAM block. M3 CPU/µDMA accesses are allowed based on the
setting of protection bits in the MSxSRCR register.
1 C28 subsystem is master for S5 RAM block. C28 CPU/DMA accesses are allowed based on the
setting of protection bits in the CSxSRCR register.
Master Ownership for S4 RAM Block
0 M3 subsystem is master for S4 RAM block. M3 CPU/µDMA accesses are allowed based on the
setting of protection bits in the MSxSRCR register.
1 C28 subsystem is master for S4 RAM block. C28 CPU/DMA accesses are allowed based on the
setting of protection bits in the CSxSRCR register.
Master Ownership for S3 RAM Block
0 M3 subsystem is master for S3 RAM block. M3 CPU/µDMA accesses are allowed based on the
setting of protection bits in the MSxSRCR register.
1 C28 subsystem is master for S3 RAM block. C28 CPU/DMA accesses are allowed based on the
setting of protection bits in the CSxSRCR register.
Master Ownership for S2 RAM Block
0 M3 subsystem is master for S2 RAM block. M3 CPU/µDMA accesses are allowed based on the
setting of protection bits in the MSxSRCR register.
1 C28 subsystem is master for S2 RAM block. C28 CPU/DMA accesses are allowed based on the
setting of protection bits in the CSxSRCR register.
Master Ownership for S1 RAM Block
0 M3 subsystem is master for S1 RAM block. M3 CPU/µDMA accesses are allowed based on the
setting of protection bits in the MSxSRCR register.
1 C28 subsystem is master for S1 RAM block. C28 CPU/DMA accesses are allowed based on the
setting of protection bits in the CSxSRCR register.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
Reserved
R-0
3 2
S3MSEL S2MSEL
R/W-0 R/W-0
RAM Control Module Registers
16
8
1 0
S1MSEL S0MSEL
R/W-0 R/W-0
Internal Memory
439